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SA9903BSA Datasheet(PDF) 6 Page - Sames |
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SA9903BSA Datasheet(HTML) 6 Page - Sames |
6 / 12 page sames sames SA9903B 6/12 http://www.sames.co.za The sequence 110 (0x06) must precede the 6-bit address of the register being accessed. When CS is HIGH, data on pin DI is clocked into the SA9903B on the rising edge of SCK. Figure 5 shows the data clocked into DI comprising of 1 1 0 A5 A4 A3 A2 A1 A0. Address locations A5 and A4 are included for compatibility with future developments. Registers may be read individually and in any order. After a register has been read, the contents of the next register value will be shifted out on the DO pin with every SCK clock cycle. Data output on DO will continue until CS is inactive. The 9 bits needed for register addressing can be padded with leading zeros when the micro-controller requires a 8 bit SPI word length. The following sequence is valid: 0000 0001 10A5A4 A3A2A1A0 DATA FORMAT Figure 5 shows the SPI waveforms. After the least significant digit of the address has been entered on the rising edge of SCK, the output DO goes low with the falling edge of SCK. Each subsequent falling edge transition on the SCK pin will validate the next data bit on the DO pin. The content of each register consists of 24 bits of data. The MSB is shifted out first. Figure 6: SPI Timing diagrams with timing information Figure 5: SPI waveforms t1 t5 t3 SCK DI DO CS DR-01545 t4 t2 1 1 A5 A0 A1 A2 A3 A4 0 D23 D22 D21 D1 D0 D23 D22 D1 D0 DO DI SCK CS Read command Register address Register Data Next data register High impedance 0 Parameter t1 t3 t4 t2 t5 Max 1.160µs Min 625ns 625ns 625ns 20ns 625ns Description SCK rising edge to DO valid SCK min high time SCK min low time Setup time for DI and CS before the rising edge of SCK DI hold time |
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