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SA9101 Datasheet(PDF) 7 Page - Sames |
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SA9101 Datasheet(HTML) 7 Page - Sames |
7 / 40 page SA9101 sames 7/40 Clock Generator Signal Pin Input/Output/Bidirect Function SCLK 24 I System Clock f=4,096 MHz/8,192MHz RFSPQ 5 O Receive Frame Pulse Frequency: 8 kHz Duration: 488 ns If loss of synchronisation, the line frame pulse is inhibited SYPQ 28 I Synchronous Pulse Defines start of frame for System internal data, together with the programmed offset values of transmit and receive counter. Pulse width: >244 ns Period: Multiples of 125µs DIU Controller Signal Pin Input/Output/Bidirect Function D0 - D7 7 - 14 B Bidirectional 8 bit data-bus A0 - A3 16 - 19 I Address lines for SA9101 internal registers CEQ 22 I Chip enable input WRQ 21 I Write enable input RDQ 20 I Read enable input COS 23 I Carrier out of service input. SA9101 sends AIS to PCM30 interface if input is at “1” XREQ 36 O Transmit DMA interrupt request RREQ 37 O Receive DMA interrupt request AINT 3 O Alarm interrupt request ACKNLQ 32 I DMA Acknowledge (Active Low) (Not used when CR6B6 = 0. If not used then pin must be fixed to V DD.) If access to internal TS16 signalling stacks is enabled this input acts as an "access enable" to the internal stacks (CRAB0-7 for T X and SR7B0-7 for R X) in conjunction with a read/write command without the need of generating the chip enable signal at CEQ. In this case it is to be connected to the acknowledge output of the DMA controller. |
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