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RV5C387A Datasheet(PDF) 13 Page - RICOH electronics devices division

Part No. RV5C387A
Description  I2C-bus Real-Time Clock ICs with Voltage Monitoring Function?
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Manufacturer  RICOH [RICOH electronics devices division]
Direct Link  http://www.ricoh.com
Logo RICOH - RICOH electronics devices division

RV5C387A Datasheet(HTML) 13 Page - RICOH electronics devices division

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PRELIMINARY
RV5C387A
12345
- 13 -
(5) /CLEN1
32-kHz Clock Output Bit 1
/CLEN1
Description
0
Enabling the 32-kHz clock output
(Default)
1
Disabling the 32-kHz clock output
Setting the /CLEN1 bit or the /CLEN2 bit (D4 in control register 1) to 0 specifies generating clock pulses with the
oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.
Conversely, setting
both the /CLEN1 bit and the /CLEN2 bit to 1 specifies disabling (“H”) such output.
(6) CTFG
Periodic Interrupt Flag Bit
CTFG
Description
0
Periodic interrupt output = “H”
(Default)
1
Periodic interrupt output = “L”
The CTFG bit is set to 1 when the periodic interrupt signals are output from the /INTRA pin (“L”).
The CTFG bit
accepts only the writing of 0 in the level mode, which disables (“H”) the /INTRA pin until it is enabled (“L”) again in
the next interrupt cycle. Conversely, setting the CTFG bit to 1 causes no event.
(7) WAFG,DAFG
Alarm_W Flag Bit and Alarm_D Flag Bit
WAFG,DAFG
Description
0
Indicating a mismatch between current time and preset alarm time
(Default)
1
Indicating a match between current time and preset alarm time
The WAFG and DAFG bits are valid only when the WALE and DALE have the setting of 1, which is caused
approximately 61
µs after any match between current time and preset alarm time specified by the Alarm_W
registers and the Alarm_D registers.
The WAFG (DAFG) bit accepts only the writing of 0.
/INTRB (/INTRC) pin
outputs off (“H”) when this bit is set to 0.
And /INTRB (/INTRC) pin outputs “L” again at the next preset alarm
time.
Conversely, setting the WAFG and DAFG bits to 1 causes no event.
The WAFG and DAFG bits will have
the reading of 0 when the alarm interrupt circuit is disabled with the WALE and DALE bits set to 0.
The settings
of the WAFG and DAFG bits are synchronized with the output of the /INTRB (/INTRC) pin as shown in the timing
chart below.
/INTRB(/INTRC) Pin
Writing of 0 to
WAFG(DAFG) bit
WAFG(DAFG) Bit
(Match between
current time and
preset alarm time)
Approx. 61
µs
Approx. 61
µs
Writing of 0 to
WAFG(DAFG) bit
(Match between
current time and
preset alarm time)
(Match between
current time and
preset alarm time)


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