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RV5C338A Datasheet(PDF) 24 Page - RICOH electronics devices division |
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RV5C338A Datasheet(HTML) 24 Page - RICOH electronics devices division |
24 / 52 page ![]() 21 R ×5C338A USAGES 1. Data Transfer Formats 1.1 Timing Between CE Pin Transition and Data Input/Output The R ×5C338A adopt a 3-wire serial interface by which it uses the CE (Chip Enable), SCLK (Serial Clock), and SIO (Serial Input/Output), pins to receive and send data to and from the CPU. The 3-wire serial interface provides two types of input/output timings with which the output and input from the SIO pin output and input are synchronized with the rising and falling edges of the SCLK pin input, respectively, and vice versa. The R ×5C338A are configured to select either one of two different input/output timings depending on the level of the SCLK pin in the low to high transition of the CE pin. Namely, when the SCLK pin is held low in the low to high transition of the CE pin, the models will select the timing with which the output and input from the SIO pin are synchronized with the rising and falling edges of the SCLK pin input, respectively, as illustrated in the timing chart below. tCES tDS tDH tRD CE SCLK SIO (Input to the real-time clock) SIO (Output from the real-time clock) Conversely, when the SCLK pin is held high in the low to high transition of the CE pin, the models will select the timing with which the output and input from the SIO pin are synchronized with the falling and rising edges of the SCLK pin input, respectively as illustrated in the timing chart below. tCES tDS tDH tRD CE SCLK SIO (Input to the real-time clock) SIO (Output from the real-time clock) |
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