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RS5C372A Datasheet(PDF) 33 Page - RICOH electronics devices division

Part No. RS5C372A
Description  I2C bus SERIAL INTERFACE REAL-TIME CLOCK ICs
Download  59 Pages
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Manufacturer  RICOH [RICOH electronics devices division]
Direct Link  http://www.ricoh.com
Logo RICOH - RICOH electronics devices division

RS5C372A Datasheet(HTML) 33 Page - RICOH electronics devices division

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RS5C372A/B
29
1.2-3 Data transmission format in I
2C bus
I
2C bus generates no CE signals. In place of it each device has a 7bit slave address allocated. The first 1byte is allo-
cated to this 7bit of slave address and to the command (R/W) for which data transmission direction is designated by
the data transmission thereafter. 7bit address is sequentially transmitted from the MSB and 2 and after bytes are
read, when 8bit is “H” and write when “L”.
The slave address of the RS5C372A/B are specified at (0110010).
At the end of data transmission/receiving stop condition is generated to complete transmission. However, if start
condition is generated without generating stop condition, repeated start condition is met and transmission/receiving
data may be continued by setting the slave address again. Use this procedures when the transmission direction
needs to be changed during one transmission.
S
Master to slave
Start condition
P
Slave to master
Stop condition
Sr Repeated start condition
A
A
Acknowledge signal
A
S
0 A
A
A P
R/W=0 (Write)
(0110010)
Data is written into
the slave from the master
When data is read from
the slave immediately
after 7bit addressing
from the master
When the transmission
direction is to be changed
during transmission.
S
1 A
A
P
R/W=1 (Read)
(0110010)
S
0 A
A Sr
1
R/W=0 (Write)
(0110010)
R/W=1 (Read)
(0110010)
A
A
P
Inform read has been completed by
not generating an acknowledge signal, to the slave side.
Inform read has been completed by
not generating an acknowledge signal,
to the slave side.
A
A
Slave address
Slave address
Slave address
Slave address
Data
Data
Data
Data
Data
Data
Data


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