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EZANPE101M Datasheet(PDF) 3 Page - Panasonic Semiconductor |
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EZANPE101M Datasheet(HTML) 3 Page - Panasonic Semiconductor |
3 / 5 page Chip Capacitor Networks Design and specifications are each subject to change without notice. Ask factory for the current technical specifications before purchase and/or use. Should a safety concern arise regarding this product, please be sure to contact us immediately. : Land pattern g c (0.20) P b t1 t2 Chip component P1 P2 P0 Compartment Sprocket hole fD0 Tape running direction A fD1 W T fA fC ● Embossed Carrier Taping ● Taping Reel ■ Packaging Methods (Taping) ● Standard Quantity ■ Recommended Land Pattern Design Type Kind of Taping Pitch (P1) Quantity EZANP Embossed Carrier Taping 4 mm 4000 pcs./reel AB W F E P0 Dimensions (mm) 3.50 ±0.20 6.80±0.20 12.00±0.30 5.50±0.20 1.75±0.20 4.00±0.10 P1 P2 fD0 t1 t2 fD1 Dimensions (mm) 4.00 ±0.10 2.00±0.05 1.50+0.10 0.25±0.05 1.30±0.20 1.50+0.10 −0 −0 Dimensions (mm) fA fB fC 180.0 +0 60 min. 13.0 ±1.0 −3.0 Dimensions (mm) WT 13.0 ±1.0 15.4 ±2.0 fg P Dimensions (mm) 4.2 to 4.6 7.5 to 7.9 1.27 abcd Dimensions (mm) 2.2 to 2.4 0.4 to 0.6 5.7 to 5.9 0.4 to 0.8 Feb. 2006 |
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