1.

General description

The SSTUB32866 is a 1.8 V configurable register specifically designed for use on DDR2

memory modules requiring a parity checking function. The register is configurable (using

configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter

configuration can be designated as Register A or Register B on the DIMM.

The SSTUB32866 accepts a parity bit from the memory controller on its parity bit

(PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs

and indicates whether a parity error has occurred on its open-drain QERR pin

(active LOW). The convention is even parity, that is, valid parity is defined as an even

number of ones across the DIMM-independent data inputs combined with the parity input

bit.

The SSTUB32866 is packaged in a 96-ball, 6

× 16 grid, 0.8 mm ball pitch LFBGA package

(13.5 mm

× 5.5 mm).

2.

Features and benefits

Configurable register supporting DDR2 up to 800 MT/s Registered DIMM applications

Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode

Controlled output impedance drivers enable optimal signal integrity and speed

Meets or exceeds SSTUB32866 JEDEC standard speed performance

Supports up to 450 MHz clock frequency of operation

Optimized pinout for high-density DDR2 module design

Chip-selects minimize power consumption by gating data outputs from changing state

Supports SSTL_18 data inputs

Checks parity on the DIMM-independent data inputs

Partial parity output and input allows cascading of two SSTUB32866s for correct parity

error processing

Differential clock (CK and CK) inputs

Supports LVCMOS switching levels on the control and RESET inputs

Single 1.8 V supply operation (1.7 V to 2.0 V)

Available in 96-ball, 13.5 mm

× 5.5 mm, 0.8 mm ball pitch LFBGA package

3.

Applications

400 MT/s to 800 MT/s DDR2 registered DIMMs desiring parity checking functionality

SSTUB32866

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer

with parity for DDR2-800 RDIMM applications

Rev. 04 — 15 April 2010

Product data sheet