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SSTUB32868 Datasheet(PDF) 4 Page - NXP Semiconductors |
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SSTUB32868 Datasheet(HTML) 4 Page - NXP Semiconductors |
4 / 30 page SSTUB32868_4 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 04 — 22 April 2010 4 of 30 NXP Semiconductors SSTUB32868 1.8 V DDR2-800 configurable registered buffer with parity (1) Register A configuration (C = 0): D1 to D5, D7, D9 to D12, D17 to D28 Register B configuration (C = 1): D1 to D12, D17 to D20, D22, D24 to D28 (2) Register A configuration (C = 0): Q1A to Q5A, Q7A, Q9A to Q12A, Q17A to Q28A Register B configuration (C = 1): Q1A to Q12A, Q17A to Q20A, Q22A, Q24A to Q28A (3) Register A configuration (C = 0): Q1B to Q5B, Q7B, Q9B to Q12B, Q17B to Q28B Register B configuration (C = 1): Q1B to Q12B, Q17B to Q20B, Q22B, Q24B to Q28B Fig 2. Parity logic diagram (positive logic) D Q R VREF Dn(1) RESET CK CK QnA(2) QnB(3) 002aac497 22 22 CLK 22 22 22 CSGEN CE D Q R PAR_IN CLK CE PARITY GENERATOR AND ERROR CHECK 22 QERR D Q R DCS0 CLK QCS0A QCS0B D Q R DCS1 CLK QCS1A QCS1B DCS2 DCS3 |
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