SSTUB32866_4

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© NXP B.V. 2010. All rights reserved.

Product data sheet

Rev. 04 — 15 April 2010

9 of 30

NXP Semiconductors

SSTUB32866

1.8 V DDR2-800 configurable registered buffer with parity

The device also supports low-power active operation by monitoring both system chip

select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states

when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn

and PPO outputs will function normally. The RESET input has priority over the DCS and

CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the

QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can

be hard-wired to ground, in which case, the set-up time requirement for DCS would be the

same as for the other Dn data inputs. To control the low-power mode with DCS only, then

To ensure defined outputs from the register before a stable clock has been supplied,

RESET must be held in the LOW state during power-up.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with

respect to CK and CK. Therefore, no timing relationship can be guaranteed between the

two. When entering reset, the register will be cleared and the Qn outputs will be driven

LOW quickly, relative to the time to disable the differential input receivers. However, when

coming out of reset, the register will become active quickly, relative to the time to enable

the differential input receivers. As long as the data inputs are LOW, and the clock is stable

during the time from the LOW to HIGH transition of RESET until the input receivers are

fully enabled, the design of the SSTUB32866 must ensure that the outputs will remain

LOW, thus ensuring no glitches on the output.

7.1 Function table

[1]

Table 4.

Function table (each flip-flop)

L = LOW voltage level; H = HIGH voltage level; X = don’t care;

Inputs

Outputs[1]

RESET

DCS

CSR

CK

CK

Dn, DODTn,

DCKEn

Qn

QCS

QODT,

QCKE

HL

L

↑↓

LL

L

L

HL

L

↑↓

HH

L

H

H

L

L

L or H

L or H

X

HL

H

↑↓

LL

L

L

HL

H

↑↓

HH

L

H

H

L

H

L or H

L or H

X

HH

L

↑↓

LL

H

L

HH

L

↑↓

HH

H

H

H

H

L

L or H

L or H

X

HH

H

↑↓

HL

HH

H

↑↓

HH

H

H

H

L or H

L or H

X

L

X or floating

X or floating

X or floating

X or floating

X or floating

L

L

L