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SSTUA32866 Datasheet(PDF) 11 Page - NXP Semiconductors |
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SSTUA32866 Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 28 page SSTUA32866_2 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 02 — 26 March 2007 11 of 28 NXP Semiconductors SSTUA32866 1.8 V DDR2-667 configurable registered buffer with parity 10. Characteristics Table 7. Characteristics At recommended operating conditions (see Table 6); unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit VOH HIGH-level output voltage IOH = −6 mA; VDD = 1.7 V 1.2 - - V VOL LOW-level output voltage IOL = 6 mA; VDD = 1.7 V - - 0.5 V II input current all inputs; VI =VDD or GND; VDD = 2.0 V - - ±5 µA IDD supply current static standby; RESET = GND; IO = 0 mA; VDD = 2.0 V -- 2 mA static operating; RESET = VDD; IO = 0 mA; VDD = 2.0 V; VI =VIH(AC) or VIL(AC) - - 40 mA IDDD dynamic operating current per MHz clock only; RESET = VDD; VI =VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. IO = 0 mA; VDD = 1.8 V -16 - µA per each data input, 1 : 1 mode; RESET = VDD; VI =VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. One data input switching at half clock frequency, 50 % duty cycle. IO = 0 mA; VDD = 1.8 V -11 - µA per each data input, 1 : 2 mode; RESET = VDD; VI =VIH(AC) or VIL(AC); CK and CK switching at 50 % duty cycle. One data input switching at half clock frequency, 50 % duty cycle. IO = 0 mA; VDD = 1.8 V -19 - µA Ci input capacitance data and CSR inputs; VI =Vref ± 250 mV; VDD = 1.8 V 2.5 - 3.5 pF CK and CK inputs; VICR = 0.9 V; Vi(p-p) = 600 mV; VDD = 1.8 V 2- 3pF RESET input; VI =VDD or GND; VDD = 1.8 V 3- 4pF |
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