Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.COM

X  

SSTUA32S865ET Datasheet(PDF) 10 Page - NXP Semiconductors

Part # SSTUA32S865ET
Description  1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-667 RDIMM applications
Download  29 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

SSTUA32S865ET Datasheet(HTML) 10 Page - NXP Semiconductors

Back Button SSTUA32S865ET Datasheet HTML 6Page - NXP Semiconductors SSTUA32S865ET Datasheet HTML 7Page - NXP Semiconductors SSTUA32S865ET Datasheet HTML 8Page - NXP Semiconductors SSTUA32S865ET Datasheet HTML 9Page - NXP Semiconductors SSTUA32S865ET Datasheet HTML 10Page - NXP Semiconductors SSTUA32S865ET Datasheet HTML 11Page - NXP Semiconductors SSTUA32S865ET Datasheet HTML 12Page - NXP Semiconductors SSTUA32S865ET Datasheet HTML 13Page - NXP Semiconductors SSTUA32S865ET Datasheet HTML 14Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 10 / 29 page
background image
SSTUA32S865_2
© NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 02 — 16 March 2007
10 of 29
NXP Semiconductors
SSTUA32S865
1.8 V DDR2-667 registered buffer with parity
7.3 Functional differences to SSTU32864
The SSTUA32S865 for its basic register functionality, signal definition and performance is
based upon the industry-standard SSTU32864, but provides key operational features
which differ (at least in part) from the industry-standard register in the following aspects:
7.3.1 Chip Select (CS) gating of key inputs (DCS0, DCS1, CSGATEEN)
As a means to reduce device power, the internal latches will only be updated when one or
both of the CS inputs are active (LOW) and CSGATEEN HIGH at the rising edge of the
clock. The 22 ‘Chip-Select-gated’ input signals associated with this function include
addresses (ADDR0 to ADDR15, BA0 to BA2), and RAS, CAS, WE, with the remaining
signals (CS, CKE, ODT) continuously re-driven at the rising edge of every clock as they
are independent of CS. The CS gating function can be disabled by tying CSGATEEN
LOW, enabling all internal latches to be updated on every rising edge of the clock.
7.3.2 Parity error checking and reporting
The SSTUA32S865 incorporates a parity function, whereby the signal received on input
pin PARIN is received as parity to the register, one clock cycle later than the CS-gated
inputs. The received parity bit is then compared to the parity calculated across these
same inputs by the register parity logic to verify that the information has not been
corrupted. The 22 CS-gated input signals will be latched and re-driven on the first clock,
and any error will be reported one clock cycle later via the PTYERR output pin (driven
LOW for two consecutive clock cycles). PTYERR is an open-drain output, allowing
multiple modules to share a common signal pin for reporting the occurrence of a parity
error during a valid command cycle (coincident with the re-driven signals). This output is
driven LOW for two consecutive clock cycles to allow the memory controller sufficient time
to sense and capture the error even. A LOW state on PTYERR indicates that a parity error
has occurred.
7.3.3 Reset (RESET)
Similar to the RESET pin on the industry-standard SSTU32864, this pin is used to clear all
internal latches and all outputs will be driven LOW quickly except the PTYERR output,
which will be floated (and will normally default HIGH by their external pull-up).
7.3.4 Power-up sequence
The reset function for the SSTUA32S865 is similar to that of the SSTU32864 except that
the PTYERR signal is also cleared and will be held clear (HIGH) for three consecutive
clock cycles.
Table 5.
Chip Select gating mode
Mode
Signal name
Description
Gating
CSGATEEN
HIGH
Registers only re-drive signals to the DRAMs when
Chip Select inputs are LOW.
Non-gating
CSGATEEN
LOW
Registers always re-drive signals on every clock cycle,
independent of the state of the Chip Select inputs.


Similar Part No. - SSTUA32S865ET

ManufacturerPart #DatasheetDescription
logo
NXP Semiconductors
SSTUA32864 PHILIPS-SSTUA32864 Datasheet
112Kb / 19P
   1.8 V configurable registered buffer for DDR2-667 RDIMM applications
Rev. 01-12 May 2005
SSTUA32864 NXP-SSTUA32864 Datasheet
124Kb / 20P
   1.8 V configurable registered buffer for DDR2-667 RDIMM applications
Rev. 02-9 March 2007
SSTUA32864EC PHILIPS-SSTUA32864EC Datasheet
112Kb / 19P
   1.8 V configurable registered buffer for DDR2-667 RDIMM applications
Rev. 01-12 May 2005
SSTUA32864EC NXP-SSTUA32864EC Datasheet
124Kb / 20P
   1.8 V configurable registered buffer for DDR2-667 RDIMM applications
Rev. 02-9 March 2007
SSTUA32864EC/G NXP-SSTUA32864EC/G Datasheet
124Kb / 20P
   1.8 V configurable registered buffer for DDR2-667 RDIMM applications
Rev. 02-9 March 2007
More results

Similar Description - SSTUA32S865ET

ManufacturerPart #DatasheetDescription
logo
NXP Semiconductors
SSTU32865 PHILIPS-SSTU32865 Datasheet
157Kb / 29P
   1.8 V 28-bit 1:2 registered buffer with parity for DDR2 RDIMM
Rev. 02-28 September 2004
SSTUB32865 NXP-SSTUB32865 Datasheet
163Kb / 28P
   1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications
Rev. 03-27 March 2007
SSTUG32865 NXP-SSTUG32865 Datasheet
162Kb / 28P
   1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-1G RDIMM applications
Rev. 01-16 August 2007
SSTUM32865 NXP-SSTUM32865 Datasheet
152Kb / 28P
   1.8 V 28-bit 1 : 2 registered buffer with parity for DDR2-800 RDIMM applications
Rev. 01-19 September 2007
SSTUM32868 NXP-SSTUM32868 Datasheet
177Kb / 30P
   1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
Rev. 02-2 March 2007
SSTUB32868 NXP-SSTUB32868 Datasheet
264Kb / 30P
   1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications
Rev. 04-22 April 2010
SSTUG32868 NXP-SSTUG32868 Datasheet
174Kb / 29P
   1.8 V 28-bit 1 : 2 configurable registered buffer with parity for DDR2-1G RDIMM applications
Rev. 01-23 April 2007
SSTUA32864 NXP-SSTUA32864_07 Datasheet
124Kb / 20P
   1.8 V configurable registered buffer for DDR2-667 RDIMM applications
Rev. 02-9 March 2007
SSTUA32866 NXP-SSTUA32866 Datasheet
161Kb / 28P
   1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications
Rev. 02-26 March 2007
SSTUA32864 PHILIPS-SSTUA32864 Datasheet
112Kb / 19P
   1.8 V configurable registered buffer for DDR2-667 RDIMM applications
Rev. 01-12 May 2005
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29


Datasheet Download

Go To PDF Page


Link URL




Privacy Policy
ALLDATASHEET.COM
Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Datasheet Upload   |   Contact us   |   Privacy Policy   |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com