74LVT16500A_3

© Koninklijke Philips Electronics N.V. 2006. All rights reserved.

Product data sheet

Rev. 03 — 29 May 2006

6 of 19

Philips Semiconductors

74LVT16500A

3.3 V 18-bit universal bus transceiver; 3-state

6.

Functional description

[1]

H = HIGH voltage level;

h = HIGH voltage level one setup time prior to the enable or clock transition;

L = LOW voltage level;

l = LOW voltage level one setup time prior to the enable or clock transition;

NC = no change;

X = don’t care;

Z = high-impedance OFF-state;

↓ = HIGH-to-LOW enable or clock transition.

B3

49

data input/output B3

50

supply voltage

B2

51

data input/output B2

B1

52

data input/output B1

GND

53

ground (0 V)

B0

54

data input/output B0

CPAB

55

A-to-B clock input (active falling edge)

GND

56

ground (0 V)

Table 2.

Symbol

Pin

Description

Table 3.

Function table[1]

Operating mode

Control

Input

Internal

register

Output

OEAB

LEAB

CPAB

An

Bn

OEBA

LEBA

CPBA

Bn

An

disabled

L

H

X

X

X

Z

disabled, latch data

L

↓

Xh

H

Z

disabled, latch data

L

↓

Xl

L

Z

disabled, hold data

L

L

H or L

X

NC

Z

disabled, clock data

L

L

↓

hH

Z

disabled, clock data

L

L

↓

lL

Z

transparent

H

H

X

H

H

H

transparent

H

H

X

L

L

L

latch data and display

H

↓

Xh

H

H

latch data and display

H

↓

Xl

L

L

clock data and display

H

L

↓

hH

H

clock data and display

H

L

↓

lL

L

hold data and display

H

L

H or L

X

H

H

hold data and display

H

L

H or L

X

L

L