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74ALVCH16501 Datasheet(PDF) 11 Page - NXP Semiconductors |
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74ALVCH16501 Datasheet(HTML) 11 Page - NXP Semiconductors |
11 / 18 page 74ALVCH16501_3 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 03 — 2 April 2010 11 of 18 NXP Semiconductors 74ALVCH16501 18-bit universal bus transceiver; 3-state Measurement points are given in Table 8. VOL and VOH are typical output levels that occur with the output load. Fig 8. Propagation delay, latch enable input (LEAB, LEBA) and clock pulse input (CPAB, CPBA) to data output, and pulse width 001aal720 tPHL tPLH tW 1 / fmax VM VM VM VM VM LExx input CPxx input An, Bn output GND VOH VOL VI Measurement points are given in Table 8. Fig 9. Data set-up and hold times (An, Bn inputs to LEAB, LEBA, CPAB and CPBA inputs) 001aal722 VM VI GND VI GND An, Bn input CPxx, LExx input VM VM tsu th tsu th VM VM VM Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 2.3 V to 2.7 V VCC 0.5 0.5 VOL + 0.15 V VOH − 0.15 V 2.7 V 2.7 V 2.7 V 1.5 V VOL + 0.3 V VOH − 0.3 V 3.0 V to 3.6 V 2.7 V 2.7 V 1.5 V VOL + 0.3 V VOH − 0.3 V |
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