SC122

10

Applications Information (continued)

A suggested very low duty cycle refresh oscillator circuit

is included on the SC122 EVB-RM, the SC122 Evaluation

Board with Refresh Modulation.

Regulator Startup, Short Circuit Protection,

and Current Limits

The SC122 permits power up at input voltages from 0.85V

to 1.6V. Startup current limiting of the internal switching

n-channel and p-channel FET power devices protects

them from damage in the event of a short between OUT

and GND. This protection prevents startup into an exces-

sive load.

At the beginning of the cycle, the p-channel FET between

the LX and OUT pins turns on with its current limited to

approximately 100mA, the short-circuit output current.

When V

OUT

approaches V

IN

(still below 1.7V), the n-channel

current limit is set to 350mA (the p-channel limit is dis-

abled), an internal oscillator turns on (approximately

200kHz), and a fixed 75% duty cycle PWM-type operation

begins. When the output voltage exceeds 1.7V, fixed fre-

quency PSAVE operation begins, with the duty cycle deter-

mined by an n-channel FET peak current limit of 350mA.

Note that startup with a regulated active load is not the

same as startup with a resistive load. The resistive load

output current increases proportionately as the output

voltage rises until it reaches V

OUT

/R

LOAD

, while a regulated

active load presents a constant load as the output voltage

rises from 0V to V

OUT

. Note also that if the load applied to

the output exceeds the startup current limit, the criterion

to advance to the next startup stage may not be achieved.

In this situation startup may pause at a reduced output

voltage until the load is reduced further.

Output Overload and Recovery

As the output load increases, the duration of each burst

increases, and the time between bursts decreases. The

output load reaches its maximum when the burst dura-

tion becomes indefinite (and the time between bursts

becomes zero). At this time, all the energy stored in the

inductor during the on-time portion of each burst cycle is

discharged into the output during off-time. The inductor

current reduces to zero just as the next on-time begins.

Above this critical maximum load, the output voltage will

decrease rapidly, and the startup current and switching

limits will be invoked in reverse order as the output

voltage falls through its various startup voltage thresh-

olds. How far the output voltage drops depends on the

load voltage vs. current characteristic.

A reduction in input voltage, such as a discharging

battery, will lower the load current at which overload

occurs. At the overload threshold, the energy stored in

the inductor at the end of each on-time is the same for all

V

IN

. But since the voltage increase above the input voltage

is greater, the available output current, I

OUT

= P/(V

OUT

- V

IN

),

must decrease.

When an overload has occurred, the load must be

decreased to permit recovery. The conditions required

for overload recovery are identical to those required for

successful initial startup.

Anti-ringing Circuitry

When both FET switches are simultaneously turned off,

an internal switch between the IN and LX pins is closed.

This provides a moderate resistance path across the

inductor to dampen the oscillations at the LX pin. This

effectively reduces EMI that can develop from the reso-

nant circuit formed by the inductor and the drain capaci-

tance at LX. The anti-ringing circuitry is disabled between

PSAVE bursts.

Inductor Selection

The inductance value primarily affects the amplitude of

inductor current ripple (

ΔI

L

). The inductor peak current

I

L-max

= I

L-avg

+

ΔI

L

/2, where I

L-avg

is the inductor current aver-

aged over a full on/off cycle, is subject to the n-channel

FET peak current limit I

LIM(N)

. The inductor average current

is equal to the output load current. Increasing inductance

reduces

ΔI

L

and therefore increases the maximum sup-

portable output current.

The performance plots of this datasheet were obtained

with L = 4.7μH. Larger values of inductance can provide

higher maximum output currents.

Any chosen inductor should have low DCR, compared to

the R

DS-ON

of the FET switches, to maintain efficiency. For

DCR << R

DS-ON

, further reduction in DCR will provide

diminishing benefit. The inductor I

SAT

value must exceed

I

LIM(N)

. The inductor self-resonant frequency should exceed