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444-2121LF Datasheet(PDF) 97 Page - List of Unclassifed Manufacturers |
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444-2121LF Datasheet(HTML) 97 Page - List of Unclassifed Manufacturers |
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97 / 104 page  FS401, FS403 PRODUCT SPECIFICATION REV. NO. 1.7 97 JANUARY 24, 2007 COPYRIGHT © 1999 FOCUS ENHANCEMENTS, INC. 7.2.6 Video Output Filters • To reduce step noise on the D/A converter outputs, and to lower EMI, consider placing the 75 Ω termination resistors and the first capacitor of the output filter close to the video output pins of the FS400. 7.2.7 Analog Power Supply Bypassing, Filtering, and Isolation • When possible, it is recommended that the analog supply voltages be fed from a linear voltage regulator. Switching power supply noise, and noise from the digital plane can induce visible artifacts into the displayed video. Always provide sufficient filtering and high frequency bypassing to insure that power supply noise is minimized for visual as well as EMI reasons. • Noise from the digital plane must be kept isolated from the analog plane. Consider using a 1 Ω to 2Ω resistor with a 100 µF capacitor as a filter network. The voltage drop to the analog plane is minimal, and this effectively minimizes clock noise from the digital plane. • It is recommended that each power supply section be isolated with a ferrite bead and a 4.7 µF capacitor. Where the power pins are so close together that the 0.1 µF bypass capacitors are adjacent, consider changing one of the adjacent capacitors to 100 to 1000pF to reduce higher frequency noise on the power supply. 7.2.8 Power and Ground Within the FS400, separate power is routed to functional sections: A/D converters, phase locked loops, D/A converters, digital processors and digital drivers. To minimize power consumption, a +3.3 volt supply is used for the external SDRAM interface and the internal line buffers. All ground pins should be connected to a common ground plane. Power pins should be segregated into analog and digital sections. Clean analog power should be applied to the VDDAD, VDDPA, VDDPF, and VDDDA pins. A 0.1 µF capacitor should be placed adjacent to each group of pins. The capacitor connected to CBYPR is critical, and it must be connected to VDDDA to minimize noise at the D/A converter outputs. Chip capacitors are recommended. Digital power may be derived from system digital +3.3 volts. If necessary insert a ferrite bead in series with the supply trace. A 47 µF capacitor should be placed across the common +3.3 VDC for V DD, VDDAD and VDDDA to act as a reservoir for heavy currents drawn by D/A converters and memory. At least one 0.1 µF capacitor should be located adjacent to V DD pins along each side of the FS400 to supply transient currents. |
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