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MCK68HC16Z1CFC16 Datasheet(PDF) 98 Page - Freescale Semiconductor, Inc

Part No. MCK68HC16Z1CFC16
Description  M68HC16Z Series
Download  500 Pages
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Maker  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
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MCK68HC16Z1CFC16 Datasheet(HTML) 98 Page - Freescale Semiconductor, Inc

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CENTRAL PROCESSING UNIT
M68HC16 Z SERIES
4-38
USER’S MANUAL
4.13.2 Exception Stack Frame
During exception processing, the contents of the program counter and condition code
register are stacked at a location pointed to by SK : SP. Unless it is altered during ex-
ception processing, the stacked PK : PC value is the address of the next instruction in
the current instruction stream, plus $0006. Figure 4-6 shows the exception stack
frame.
Figure 4-6 Exception Stack Frame Format
Table 4-5 Exception Vector Table
Vector
Number
Vector
Address
Address
Space
Type of
Exception
0
0000
P
Reset — Initial ZK, SK, and PK
0002
P
Reset — Initial PC
0004
P
Reset — Initial SP
0006
P
Reset — Initial IZ (Direct Page)
4
0008
D
Breakpoint
5
000A
D
Bus Error
6
000C
D
Software Interrupt
7
000E
D
Illegal Instruction
8
0010
D
Division by Zero
9 – E
0012 – 001C
D
Unassigned, Reserved
F
001E
D
Uninitialized Interrupt
10
0020
D
Unassigned, Reserved
11
0022
D
Level 1 Interrupt Autovector
12
0024
D
Level 2 Interrupt Autovector
13
0026
D
Level 3 Interrupt Autovector
14
0028
D
Level 4 Interrupt Autovector
15
002A
D
Level 5 Interrupt Autovector
16
002C
D
Level 6 Interrupt Autovector
17
002E
D
Level 7 Interrupt Autovector
18
0030
D
Spurious Interrupt
19 – 37
0032 – 006E
D
Unassigned, Reserved
38 – FF
0070 – 01FE
D
User-Defined Interrupts
Low Address
⇐ SP After Exception Stacking
Condition Code Register
High Address
Program Counter
⇐ SP Before Exception Stacking
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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