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MCK68HC16Z1CFC16 Datasheet(PDF) 97 Page - Freescale Semiconductor, Inc

Part No. MCK68HC16Z1CFC16
Description  M68HC16Z Series
Download  500 Pages
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Maker  FREESCALE [Freescale Semiconductor, Inc]
Homepage  http://www.freescale.com
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MCK68HC16Z1CFC16 Datasheet(HTML) 97 Page - Freescale Semiconductor, Inc

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M68HC16 Z SERIES
CENTRAL PROCESSING UNIT
USER’S MANUAL
4-37
Total execution time is calculated using the expression:
Where:
(CLT) = Total clock periods per instruction
(CLI) = Clock periods used for internal operation
(CLP) = Clock periods used for program access
(CLO) = Clock periods used for operand access
Refer to the
CPU16 Reference Manual (CPU16RM/AD) for more information on this
topic.
4.13 Exceptions
An exception is an event that preempts normal instruction processing. Exception pro-
cessing makes the transition from normal instruction execution to execution of a rou-
tine that deals with the exception.
Each exception has an assigned vector that points to an associated handler routine.
Exception processing includes all operations required to transfer control to a handler
routine, but does not include execution of the handler routine itself. Keep the distinc-
tion between exception processing and execution of an exception handler in mind
while reading this section.
4.13.1 Exception Vectors
An exception vector is the address of a routine that handles an exception. Exception
vectors are contained in a data structure called the exception vector table, which is lo-
cated in the first 512 bytes of bank 0. Refer to Table 4-5 for the exception vector table.
All vectors except the reset vector consist of one word and reside in data space. The
reset vector consists of four words that reside in program space. Refer to SECTION 5
SYSTEM INTEGRATION MODULE for information concerning address space types
and the function code outputs. There are 52 predefined or reserved vectors, and 200
user-defined vectors.
Each vector is assigned an 8-bit number. Vector numbers for some exceptions are
generated by external devices; others are supplied by the processor. There is a direct
mapping of vector number to vector table address. The processor left shifts the vector
number one place (multiplies by two) to convert it to an address.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com


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