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MCK68HC16Z1CFC16 Datasheet(PDF) 94 Page - Freescale Semiconductor, Inc |
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MCK68HC16Z1CFC16 Datasheet(HTML) 94 Page - Freescale Semiconductor, Inc |
94 / 500 page CENTRAL PROCESSING UNIT M68HC16 Z SERIES 4-34 USER’S MANUAL Figure 4-4 Basic Instruction Formats 4.10 Execution Model This description builds up a conceptual model of the mechanism the CPU16 uses to fetch and execute instructions. The functional divisions in the model do not necessarily correspond to physical subunits of the microprocessor. As shown in Figure 4-5, there are three functional blocks involved in fetching, decod- ing, and executing instructions. These are the microsequencer, the instruction pipe- line, and the execution unit. These elements function concurrently. All three may be active at any given time. 8-Bit Opcode with 8-Bit Operand 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode Operand 8-Bit Opcode with 4-Bit Index Extensions 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode X Extension Y Extension 8-Bit Opcode, Argument(s) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode Operand Operand(s) Operand(s) 8-Bit Opcode with 8-Bit Prebyte, No Argument 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Prebyte Opcode 8-Bit Opcode with 8-Bit Prebyte, Argument(s) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Prebyte Opcode Operand(s) Operand(s) 8-Bit Opcode with 20-Bit Argument 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Opcode $0 Extension Operand Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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