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XIO3130I Datasheet(PDF) 9 Page - Texas Instruments |
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XIO3130I Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 142 page  XIO3130 www.ti.com SLLS693F – MAY 2007 – REVISED JANUARY 2010 4-31 Bit Descriptions – Serial Bus Slave Address Register ...................................................................... 60 4-32 Bit Descriptions – Serial Bus Control and Status Register ................................................................. 60 4-33 Bit Descriptions – Upstream Port Link PM Latency Register .............................................................. 62 4-34 Bit Descriptions – Global Chip Control Register ............................................................................. 63 4-35 Bit Descriptions – GPIO A Control Register ................................................................................. 65 4-36 Bit Descriptions – GPIO B Control Register ................................................................................. 67 4-37 Bit Descriptions – GPIO C Control Register ................................................................................. 69 4-38 Bit Descriptions – GPIO D Control Register .................................................................................. 71 4-39 Bit Descriptions – GPIO Data Register ........................................................................................ 72 4-40 Bit Descriptions – Subsystem Access Register ............................................................................. 77 4-41 Bit Descriptions – General Control Register ................................................................................. 77 4-42 Bit Descriptions – Downstream Ports Link PM Latency Register ......................................................... 78 4-43 Bit Descriptions – Global Switch Control Register .......................................................................... 79 4-44 Uncorrectable Error Status Register .......................................................................................... 81 4-45 Uncorrectable Error Mask Register ........................................................................................... 81 4-46 Uncorrectable Error Severity Register ........................................................................................ 83 4-47 Correctable Error Status Register ............................................................................................. 84 4-48 Correctable Error Mask Register .............................................................................................. 84 4-49 Advanced Error Capabilities and Control Register .......................................................................... 85 4-50 PCI Express Downstream Port Configuration Register Map (Type 1) .................................................... 87 4-51 Extended Configuration Space (Downstream Port) .......................................................................... 88 4-52 Bit Descriptions – Command Register ........................................................................................ 89 4-53 Bit Descriptions – Status Register ............................................................................................. 89 4-54 Bit Descriptions – Class Code and Revision ID Register .................................................................. 90 4-55 Bit Descriptions – I/O Base Register .......................................................................................... 93 4-56 Bit Descriptions – I/O Limit Register .......................................................................................... 93 4-57 Bit Descriptions – Secondary Status Register ............................................................................... 94 4-58 IBit Descriptions – Memory Base Register ................................................................................... 94 4-59 Bit Descriptions – Memory Limit Register .................................................................................... 95 4-60 Descriptions – Pre-fetchable Memory Base Register ....................................................................... 95 4-61 Bit Descriptions – Pre-fetchable Memory Limit Register ................................................................... 96 4-62 Bit Descriptions – Pre-fetchable Base Upper 32 Bits Register ............................................................ 96 4-63 Descriptions – Pre-fetchable Limit Upper 32 Bits Register ................................................................ 96 4-64 Bit Descriptions – I/O Base Upper 16 Bits Register ........................................................................ 97 4-65 Bit Descriptions – I/O Limit Upper 16 Bits Register ......................................................................... 97 4-66 Bit Descriptions – Bridge Control Register ................................................................................... 98 4-67 Bit Descriptions – Power Management Capabilities Register ............................................................ 100 4-68 Bit Descriptions – Power Management Control/Status Register ......................................................... 101 4-69 Bit Descriptions – PM Bridge Support Extension Register ............................................................... 102 4-70 Bit Descriptions – MSI Message Control Register ......................................................................... 103 4-71 Bit Descriptions – MSI Message Address Register ....................................................................... 104 4-72 Bit Descriptions – MSI Data Register ....................................................................................... 104 4-73 Bit Descriptions – PCI Express Capabilities Register ..................................................................... 107 4-74 Bit Descriptions – Device Capabilities Register ............................................................................ 108 4-75 Bit Descriptions – Device Control Register ................................................................................. 108 4-76 Bit Descriptions – Device Status Register .................................................................................. 110 4-77 Bit Descriptions – Link Capabilities Register ............................................................................... 110 4-78 Bit Descriptions – Link Control Register .................................................................................... 111 Copyright © 2007–2010, Texas Instruments Incorporated List of Tables 9 |
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