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XIO2213A Datasheet(PDF) 81 Page - Texas Instruments

Part # XIO2213A
Description  PCI Express to 1394b OHCI with 3-Port PHY
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

XIO2213A Datasheet(HTML) 81 Page - Texas Instruments

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4.66 General Control Register
XIO2213A PCI Express to 1394b OHCI with 3-Port PHY
www.ti.com
SCPS183A – OCTOBER 2007 – REVISED MARCH 2008
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 4-39. Subsystem Access Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:16(1)
SubsystemID
RW
Subsystem ID. The value written to this field is aliased to the subsystem ID register at PCI
offset 86h (see Section 4.46).
15:0(1)
SubsystemVendorID
RW
Subsystem vendor ID. The value written to this field is aliased to the subsystem vendor ID
register at PCI offset 84h (seeSection 4.45).
(1)
This register shall only be reset by a Fundamental Reset (FRST).
This read/write register controls various functions of the bridge. See Table 4-40 for a complete description
of the register contents.
PCI register offset:
D4h
Register type:
Read-only, Read/Write
Default value:
8600 025Fh
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
1
0
0
1
0
1
1
1
1
1
Table 4-40. General Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:30(1)
CFG_RETRY
RW
Configuration retry counter. Configures the amount of time that a configuration request must be
_CNTR
retried on the secondary PCI bus before it may be completed with configuration retry status on
the PCI Express side.
00 = 25
µs
01 = 1 ms
10 = 25 ms (default)
11 = 50 ms
29:28
ASPM_CTRL_DE
RW
Active State Power Management Control Default Override. These bits are used to determine the
F_OVRD
power up default for bits 1:0 of the Link Control Register in the PCI Express Capability Structure.
00 = Power on default indicates that the active state power management is disable (00b)
01 = (default)
10 = Power on default indicates that the active state power management is enabled for L0s
11 = (01b)
Power on default indicates that the active state power management is enabled for L1s
(10b)
Power on default indicates that the active state power management is enabled for L0s
and L1s (11b)
27(1)
LOW_POWER
RW
Low-power enable. When this bit is set, the half-ampitude, no preemphasis mode for the PCI
_EN
Express TX drivers is enabled. The default for this bit is 0b.
26(1)
PCI_PM_
RW
PCI power management version control. This bit controls the value reported in bits 2:0
VERSION_ CTRL
(PM_VERSION) in the power management capabilities register (offset 52h, see Section 4.33). It
also controls the value of bit 3 (NO_SOFT_RESET) in the power management control/status
register (offset 54h, see Section 4.34).
0 = Version fields reports 010b and NO_SOFT_RESET reports 0b for Power
Management 1.1 compliance
1 = Version fields reports 011b and NO_SOFT_RESET reports 1b for Power
Management 1.2 compliance (default)
(1)
This register shall only be reset by a Fundamental Reset (FRST).
Submit Documentation Feedback
Classic PCI Configuration Space
81


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