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UCD9224 Datasheet(PDF) 8 Page - Texas Instruments |
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UCD9224 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 36 page UCD9224 33 32 31 30 29 28 27 26 25 3 4 5 6 7 8 9 10 11 12 34 RESET Vin/Iin FLT-1B SRE-1A PMBus _Data FLT-2A PMBus _CLK DPWM -1A TMS TRST TDI / Sync _In TDO / Sync _Out TCK PGood FLT-3A DGND 1 CS-2A FLT-1A V33 A V33 D 1 2 CS-1B CS-3A 35 36 AGND 1 BPCap UCD9224 SLVSA35 – JANUARY 2010 www.ti.com The UCD9224 is available in an 48-pin QFP package (RGZ). Figure 3. Pin Assignment Diagram TYPICAL APPLICATION SCHEMATIC Figure 4 shows the UCD9224 power supply controller as part of a system that provides the regulation of one eight-phase power supply. The loop for the power supply is created by the voltage output feeding into the differential voltage error ADC (EADC) input, and completed by DPWM outputs feeding into the gate drivers for each power stage (PTD modules in this example). The ±VsA and ±VsB signal must be routed to the EAp/EAn input that matches the number of the lowest DPWM configured as part of the rail. (See more detail in Flexible Rail/Power Stage Configuration.) 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated |
Similar Part No. - UCD9224_1 |
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Similar Description - UCD9224_1 |
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