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UCC28950PW Datasheet(PDF) 26 Page - Texas Instruments |
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UCC28950PW Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 45 page  CLK SYNC_OUT A B CLK SYNC_IN A B UCC28950 SLUSA16A – MARCH 2010 – REVISED JULY 2010 www.ti.com Synchronization (SYNC) The UCC28950 allows flexible configuration of converters operating in synchronized mode by connecting all SYNC pins together and by configuration of the controllers as master and/or slaves. The controller configured as Master (resistor between RT and VREF) provides synchronization pulses at the SYNC pin with the frequency equal to 2X the converter frequency FSW(nom) and 0.5 duty cycle. The controller configured as a Slave (resistor between RT and GND and 825-k Ω resistor between SS_EN pin to GND) does not generate the synchronization pulses. The Slave controller synchronizes its own clock to the falling edge of synchronization signal thus operating 90° phase shifted versus the master converter’s frequency FSW(nom). Because the Slave is synchronized to the falling edge of the SYNC pulses, the slave operates at 180 ˚ delayed versus Master’s CLK or 90 ˚ delayed versus output switching pulses of Master. Such operation between Master and Slave provides maximum input capacitor and output capacitor ripple cancellation effect if inputs and outputs of converters are tied together. To avoid system issues during the synchronized operation of few converters the following conditions should be taken care of. • If any converter is configured a as a Slave, the SYNC frequency must be greater than or equal to 1.8 times the converter frequency. • Slave converter does not start until at least one synchronization pulse has been received. • If any or all converters are configured as Slaves, then each converter operates at its own frequency without synchronization after receiving at least one synchronization pulse. Thus, If there is an interruption of synchronization pulses at the slave converter, then the controller uses its own internal clock pulses to maintain operation based on the RT value that is connected to GND in the Slave converter. • In Master mode, SYNC pulses start after SS pin passes its Enable threshold which is 0.55 V. • Slave starts generating SS/EN voltage even though synchronization pulses have not been received. • It is recommended that the SS on the Master controller starts before the SS on the Slave controller; therefore SS/EN pin on master converter must reach its Enable threshold voltage before SS/EN on the slave converter starts for proper operation. On the same note, it’s recommended that TMIN resistors on both Master and Slave are set at the same value. Figure 18. SYNC_OUT (Master Mode) Timing Diagram Figure 19. SYNC_IN (Slave Mode) Timing Diagram 26 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): UCC28950 |
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