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EP3SE80 Datasheet(PDF) 42 Page - Altera Corporation

Part No. EP3SE80
Description  Stratix III Device Handbook, Volume 2
Download  341 Pages
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Maker  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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EP3SE80 Datasheet(HTML) 42 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
Figure 1–4 shows the setup and hold timing diagram for input registers.
For output timing, different I/O standards require different baseline loading
techniques for reporting timing delays. Altera characterizes timing delays with the
required termination for each I/O standard and with 0 pF (except for PCI and PCI-X,
which use 10 pF) loading. The timing is specified up to the output pin of the FPGA
device. The Quartus II software calculates I/O timing for each I/O standard with a
default baseline loading as specified by the I/O standards.
The following measurements are made during device characterization. Altera
measures clock-to-output delays (tco) at worst-case process, minimum voltage, and
maximum temperature (PVT) for default loading conditions listed in Table 1–37 on
page 1–34. The following equation describes clock-pin-to-output-pin timing for
Stratix III devices.
The tco from the clock pin to the I/O pin =
+ delay from the clock pad to the I/O output register
+ IOE output register clock-to-output delay
+ delay from the output register to the output pin
Figure 1–5 shows the output register clock to output timing diagram.
Simulation using IBIS models is required to determine the delays on the PCB traces in
addition to the output pin delay timing reported by the Quartus II software and the
timing model in the Stratix III Device Handbook. Perform the following steps:
1. Simulate the output driver of choice into the generalized test setup using values
from Table 1–37.
2. Record the time to VMEAS at the far end of the PCB trace.
3. Simulate the output driver of choice into the actual PCB trace and load using the
appropriate IBIS model or capacitance value to represent the load.
4. Record the time to VMEAS at the far end of the PCB trace.
Figure 1–4. Input Register Setup and Hold Timing Diagram
Input Data Delay
Input Clock Delay
micro tsu
micro th
Figure 1–5. Output Register Clock to Output Timing Diagram
Output Register to
output pin delay
Clock
Datain
Clock pad to output
Register delay
Output Register
micro tCO
Output


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