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EP3SE80 Datasheet(PDF) 40 Page - Altera Corporation

Part No. EP3SE80
Description  Stratix III Device Handbook, Volume 2
Download  341 Pages
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Maker  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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EP3SE80 Datasheet(HTML) 40 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
OCT Calibration Block Specifications
Table 1–34 lists the on-chip termination calibration block specifications for Stratix III
devices.
DCD Specifications
Table 1–35 lists the worst case duty cycle distortion for Stratix III devices.
I/O Timing
The following sections describe the timing models, preliminary and final timings, I/O
timing measurement methodology, I/O default capacitive loading, programmable
IOE delay, programmable output buffer delay, user I/O timing, and dedicated clock
pin timing.
Timing Model
The DirectDrive technology and MultiTrack interconnect ensure predictable
performance, accurate simulation, and accurate timing analysis across all Stratix III
device densities and speed grades. This section describes the performance of the
Stratix III device I/Os.
All specifications except the fast model are representative of worst-case supply
voltage and junction temperature conditions. Fast model specifications are
representative of best case process, supply voltage, and junction temperature
conditions.
The timing numbers listed in this section are extracted from the Quartus II software
version 8.1.
Table 1–34. On-Chip Termination Calibration Block Specification
Symbol
Description
Min
Typical
Max
Unit
OCTUSRCLK
Clock required by OCT calibration blocks
20
MHz
t
OCTCAL
Number of OCTUSRCLK clock cycles required
for OCT Rs and Rt calibration
1000
cycles
t
OCTSHIFT
Number of OCTUSRCLK clock cycles required
for OCT code to shift out per OCT calibration block
28
cycles
t
RS_RT
Time required to dynamically switch from Rs to Rt
2.5
ns
Table 1–35. Duty Cycle Distortion on Stratix III I/O Pins (Note 1)
Symbol
C2
C3
C4
Unit
Min
Max
Min
Max
Min
Max
Output Duty Cycle
45
55
45
55
45
55
%
Note to Table 1–35:
(1) The DCD specification applies to clock outputs from the PLLs, global clock tree, and IOE driving dedicated and
general-purpose I/O pins.


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