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EP3SE80 Datasheet(PDF) 38 Page - Altera Corporation

Part No. EP3SE80
Description  Stratix III Device Handbook, Volume 2
Download  341 Pages
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Maker  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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EP3SE80 Datasheet(HTML) 38 Page - Altera Corporation

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1–28
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Switching Characteristics
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
DLL and DQS Logic Block Specifications
Table 1–30 lists the DLL frequency range specifications for Stratix III devices.
QDRII/II+ SRAM
1.8-V
HSTL
×9, ×18,
×36
259
276
260
385
280
418
280
418
380
518
QDRII/II+ SRAM
Emulation (2)
1.8-V
HSTL
×36
279
296
280
405
300
438
300
438
400
538
RLDRAM II
1.5-V
HSTL
×9, ×18
290
278
292
388
315
421
315
421
415
521
RLDRAM II
1.8-V
HSTL
×9, ×18
259
276
260
385
280
418
280
418
380
518
Notes to Table 1–29:
(1) The values apply to Column I/Os, Row I/Os, and Hybrid mode interfaces. Column I/Os refer to top and bottom I/Os. Hybrid mode refers to DQ/DQS groups
wrapping over Column I/Os and Row I/Os of the device.
(2) For implementation, refer to the “Supporting ×36 QDRII+/QDRII SRAM Interfaces in the F780 and F1152-Pin Packages” section in the External Memory
Interfaces in Stratix III Devices chapter.
Table 1–29. Transmitter Channel-to-Channel Skew (TCCS)—Write Side (Note 1) (Part 2 of 2)
Memory Type
I/O
Standard
Width
C2
C3, I3
C4, I4
C4L, I4L
C4L, I4L
V
CCL = 1.1 V
V
CCL = 1.1 V
V
CCL = 1.1 V
VCCL = 1.1 V
VCCL = 0.9 V
TCCS (ps)
TCCS (ps)
TCCS (ps)
TCCS (ps)
TCCS (ps)
Lead
Lag
Lead
Lag
Lead
Lag
Lead
Lag
Lead
Lag
Table 1–30. DLL Frequency Range Specifications for Stratix III Devices
Frequency
Mode
Frequency Range (MHz)
Available Phase Shift
Number of
Delay Chains
DQS Delay
Buffer Mode (1)
C2
C3, I3
C4, I4
C4L, I4L
0
90 – 150
90 – 140
90 – 120
90 – 120
22.5°, 45°, 67.5°, 90°
16
Low
1
120 – 200
120 – 190
120 – 170
120 – 170
30°, 60°, 90°, 120°
12
Low
2
150 – 240
150 – 230
150 – 200
150 – 200
36°, 72°, 108°, 144°
10
Low
3
180 – 300
180 – 290
180 – 250
180 – 250
45°, 90°,135°, 180°
8
Low
4
240 – 370
240 – 350
240 – 310
240 – 310
30°, 60°, 90°,120°
12
High
5
290 – 450
290 – 420
290 – 370
290 – 370
36°, 72°, 108°, 144°
10
High
6
360 – 560
360 – 530
360 – 460
360 – 460
45°, 90°, 135°, 180°
8
High
7
470 – 740
470 – 700
470 – 610
470 – 610
60°, 120°, 180°, 240°
6
High
Note to Table 1–30:
(1) “Low” indicates a 6-bit DQS delay setting; “high” indicates a 5-bit DQS delay setting.


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