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EP3SE80 Datasheet(PDF) 33 Page - Altera Corporation

Part No. EP3SE80
Description  Stratix III Device Handbook, Volume 2
Download  341 Pages
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Maker  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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EP3SE80 Datasheet(HTML) 33 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–23
Switching Characteristics
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
Table 1–26 lists the DPA lock time specifications for Stratix III devices.
Non DPA Mode
Sampling Window
300
300
300
300
ps
Notes to Table 1–25:
(1) When J = 3 to 10, the SERDES block is used.
(2) When J = 1 or 2, the SERDES block is bypassed.
(3) Clock Boost Factor (W) is the ratio between the input data rate to the input clock rate.
(4) The minimum and maximum specification depends on the clock source (for example, the PLL and clock pin) and the clock routing resource (global, regional, or
local) used. The I/O differential buffer and input register do not have a minimum toggle rate.
(5) The t
xJitter specification is for the true LVDS I/O standard only.
(6) You can estimate the achievable maximum data rate for non-DPA mode by performing link timing closure analysis. Consider the board skew margin, transmitter
delay margin, as well as the receiver sampling margin to determine the maximum data rate supported.
(7) This is achieved by using the LVDS and DPA clock network.
(8) If the receiver (with DPA enabled) and the transmitter are using shared PLLs, the minimum data rate is 150 Mbps.
(9) This is only applied to DPA and Soft-CDR modes.
Table 1–25. True and Emulated LVDS Specifications for Stratix III Devices (Note 1), (2) (Part 3 of 3)
Symbol
Conditions
C2
C3, I3
C4, I4
C4L, I4L
Table 1–26. DPA Lock Time Specifications for Stratix III Devices (Note 1), (2), (3) (Part 1 of 2)
Standard
Training
Pattern
Number of
Data
Transitions
in one
Repetition
of Training
Pattern
Number of
repetitions
per 256
Data
Transition
(4)
Condition (5)
Min
Typ
Max
SPI-4
0000000000
1111111111
2128
without DPA
PLL calibration
256 data transitions
with DPA PLL
calibration
3×256 data transitions +
2×96 slow clock cycles
(6)
——
Parallel Rapid
I/O
00001111
2
128
without DPA
PLL calibration
256 data transitions
with DPA PLL
calibration
3×256 data transitions +
2×96 slow clock cycles
(6)
——
10010000
4
64
without DPA
PLL calibration
256 data transitions
with DPA PLL
calibration
3×256 data transitions +
2×96 slow clock cycles
(6)
——


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