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EP3SE80 Datasheet(PDF) 31 Page - Altera Corporation

Part No. EP3SE80
Description  Stratix III Device Handbook, Volume 2
Download  341 Pages
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Maker  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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EP3SE80 Datasheet(HTML) 31 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–21
Switching Characteristics
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
Periphery Performance
This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfacing, such as the LVDS high-speed
I/O interface, external memory interface, and the PCI/PCI-X bus interface. For
example, Stratix III devices I/O configured with voltage referenced I/O standards can
achieve up to the stated system interfacing speed as indicated in “External Memory
Interface Specifications” on page 1–25. General-purpose I/O standards such as 3.3,
3.0, 2.5, 1.8, or 1.5 LVTTL/LVCMOS are capable of typical 167 MHz and 1.2 LVCMOS
at 100MHz interfacing frequency with 10pF load.
1 Actual achievable frequency depends on design- and system-specific factors. You
must perform HSPICE/IBIS simulations based on your specific design and system
setup to determine the maximum achievable frequency in your system.
High-Speed I/O Specifications
Refer to the “Glossary” on page 1–326 for the definitions of the high-speed timing
specifications.
Table 1–25 lists the true and emulated LVDS specifications for Stratix III devices.
Table 1–25. True and Emulated LVDS Specifications for Stratix III Devices (Note 1), (2) (Part 1 of 3)
Symbol
Conditions
C2
C3, I3
C4, I4
C4L, I4L
f
HSCLK_in
(input clock
frequency)—True
Differential I/O
Standards
Clock boost
factor W = 1 to 40
(3)
5
800
5
717
5
717
5
717
MHz
f
HSCLK_in
(input clock
frequency)—Single
Ended I/O
Standards (9)
Clock boost
factor W = 1 to 40
(3)
5
800
5
717
5
717
5
717
MHz
f
HSCLK_out
(output clock
frequency)
5
800 (7)
5
717 (7)
5
717 (7)
5
717 (7)
MHz
Transmitter
fHSDR (data rate)
SERDES factor
J = 3 to 10 (8)
(4)
1600
(4)
1250
(4)
1250
(4)
1250
Mbps
SERDES factor
J = 2, Uses
DDR Register
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
Mbps
SERDES factor
J = 1, Uses SDR
Register
(4)
(4)
(4)
(4)
(4)
(4)
(4)
(4)
Mbps
LVDS_E_3R -fHSDR
(data rate)
SERDES factor
J = 4 to 10
(4)
1100
(4)
1100
(4)
—800
(4)
800
Mbps


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