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EP3SE80 Datasheet(PDF) 30 Page - Altera Corporation |
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EP3SE80 Datasheet(HTML) 30 Page - Altera Corporation |
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30 / 341 page  1–20 Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics Switching Characteristics Stratix III Device Handbook, Volume 2 © July 2010 Altera Corporation Configuration and JTAG Specifications Table 1–23 lists the Stratix III configuration mode specifications. Table 1–24 lists the JTAG timing parameters and values for Stratix III devices. Refer to the figure for “HIGH-SPEED I/O Block” in the “Glossary” on page 1–326 for the JTAG timing requirements. M144K (3), (5) Simple dual-port 2K × 64 (with ECC) 0 1 255 210 180 180 130 195 180 120 MHz Min Pulse Width (Clock High Time) — — 800 1000 1100 1100 1800 1000 1100 1800 ps Min Pulse Width (Clock Low Time) — — 500 625 690 690 1100 625 690 1100 ps Notes to Table 1–22: (1) Use a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle to achieve the maximum memory block performance. Use the Quartus II software to report timing for this and other memory block clocking schemes. (2) The F max shown for M9K degrades 2% when you use the Error Detection CRC feature on the device, except for the C4L speed grade with VCCL = 0.9 V. For the C4L speed grade with V CCL = 0.9V, there is no degradation in F max when you use the Error Detection CRC feature. (3) The F max shown for M144K degrades 10 MHz when you use byte-enable support on M144K. (4) Fmax is applicable when the COMPTABILITY option is turned ON. (5) Fmax is applicable when the COMPTABILITY option is turned OFF. This option is turned ON by default in Quartus II software. (6) The Fmax for the EP3SL200, EP3SE260, and EP3SL340 devices at the C2 speed grade is 7% slower than the C2 values shown in the table. Table 1–22. TriMatrix Memory Block Performance Specifications for Stratix III Devices (Note 1) (Part 3 of 3) Memory Block Type Mode ALUTs TriMatrix Memory C2 (6) C3 C4 C4L I3 I4 I4L Unit V CCL = 1.1 V V CCL = 1.1 V V CCL = 1.1 V V CCL = 1.1 V V CCL = 0.9 V V CCL= 1.1 V V CCL= 1.1 V V CCL= 0.9 V Table 1–23. Configuration Mode Specifications for Stratix III Devices (Note 1) Programming Mode DCLK F max Unit Passive Serial 100 MHz Fast Passive Parallel (2) 100 MHz Fast Active Serial (3) 40 MHz Notes to Table 1–23: (1) DCLK Fmax is restricted when you enable the Remote Update feature. For more information, refer to the Remote Update Circuitry (ALTREMOTE_UPDATE) Megafunction User Guide. (2) The data rate must be 4× slower than the clock when you use decompression and/or encryption. (3) For more information about the minimum and typical DCLK Fmax value in Fast Active Serial configuration, refer to the Configuring Stratix III Devices chapter. Table 1–24. JTAG Timing Parameters and Values for Stratix III Devices Symbol Parameter Min Max Unit t JCP TCK clock period 30 — ns t JCH TCK clock high time 14 — ns t JCL TCK clock low time 14 — ns t JPSU (TDI) JTAG port setup time for TDI 1 — ns t JPSU (TMS) JTAG port setup time for TMS 3 — ns t JPH JTAG port hold time 5 — ns t JPCO JTAG port clock to output — 11 ns t JPZX JTAG port high impedance to valid output — 14 ns t JPXZ JTAG port valid output to high impedance — 14 ns |
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