(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(2) This specification is limited by the lower of the two: I/O f
max or fout of the PLL.
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 120 ps.
(4) FREF is fIN/N when N = 1.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps
(6) High bandwidth PLL settings are not supported in external feedback mode.
(7) The cascaded PLL specification is only applicable with the following conditions:
a) Upstream PLL: 0.59 MHz
Upstream PLL BW < 1 MHz
b) Downstream PLL: Downstream PLL BW > 2 MHz
(8) External memory interface clock output jitter specifications use a different measurement method and are available in Table 1–33 on page 1–29.
Table 1–20. PLL Specifications for Stratix III Devices (Part 3 of 3)