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EP3SE80 Datasheet(PDF) 26 Page - Altera Corporation

Part No. EP3SE80
Description  Stratix III Device Handbook, Volume 2
Download  341 Pages
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Maker  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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EP3SE80 Datasheet(HTML) 26 Page - Altera Corporation

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t
OUTCCJ_IO (5), (8)
Cycle to Cycle Jitter for clock
output on regular IO
(F
OUT 100 MHz)
600
600
600
600
750
ps (p-p)
Cycle to Cycle Jitter for clock
output on regular IO
(F
OUT <100 MHz)
——
60
——
60
60
—60
—75
mUI
(p-p)
tCASC_OUTPJ_DC (5),
(7)
Period Jitter for dedicated clock
output in cascaded PLLs (F
OUT
100 MHz)
250
250
250
250
325
ps (p-p)
Period Jitter for dedicated clock
output in cascaded PLLs (F
OUT
100 MHz)
——
25
——
25
25
—25
32.5
mUI
(p-p)
f
DRIFT
Frequency drift after PFDENA is
disabled for duration of 100
s
±10
±10
±10
±10
±10
%
Notes to Table 1–20:
(1) This specification is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O standard.
(2) This specification is limited by the lower of the two: I/O f
max or fout of the PLL.
(3) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source, which is less than 120 ps.
(4) FREF is fIN/N when N = 1.
(5) Peak-to-peak jitter with a probability level of 10–12 (14 sigma, 99.99999999974404% confidence level). The output jitter specification applies to the intrinsic jitter of the PLL, when an input jitter of 30 ps
is applied.
(6) High bandwidth PLL settings are not supported in external feedback mode.
(7) The cascaded PLL specification is only applicable with the following conditions:
a) Upstream PLL: 0.59 MHz
 Upstream PLL BW < 1 MHz
b) Downstream PLL: Downstream PLL BW > 2 MHz
(8) External memory interface clock output jitter specifications use a different measurement method and are available in Table 1–33 on page 1–29.
Table 1–20. PLL Specifications for Stratix III Devices (Part 3 of 3)
Symbol
Parameter
C2
C3, I3
C4, I4
C4L, I4L
Unit
V
CCL = 1.1 V
V
CCL = 1.1 V
V
CCL = 1.1 V
V
CCL = 1.1 V
V
CCL = 0.9 V
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max


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