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EP3SE80 Datasheet(PDF) 25 Page - Altera Corporation

Part No. EP3SE80
Description  Stratix III Device Handbook, Volume 2
Download  341 Pages
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Maker  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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EP3SE80 Datasheet(HTML) 25 Page - Altera Corporation

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f
CLBW
PLL closed-loop low bandwidth
0.3
0.3
0.3
0.3
0.3
MHz
PLL closed-loop medium
bandwidth
1.5
1.5
1.5
1.5
1.5
MHz
PLL closed-loop high bandwidth
(6)
—4
4
—4
4
4
—MHz
t
PLL_PSERR
Accuracy of PLL phase shift
±50
±50
±50
±50
±50
ps
t
ARESET
Minimum pulse width on areset
signal
10
——
10
10
—10
—10
ns
t
INCCJ (3), (4)
Input clock cycle to cycle jitter
(F
REF  100 MHz)
0.15
0.15
0.15
0.15
0.1
UI (p-p)
Input clock cycle to cycle jitter
(F
REF < 100 MHz)
±750
±750
±750
±750
±500 ps (p-p)
t
OUTPJ_DC (5)
Period Jitter for dedicated clock
output (F
OUT 100 MHz)
175
175
175
175
225
ps (p-p)
Period Jitter for dedicated clock
output (F
OUT < 100 MHz)
17.5
17.5
17.5
17.5
22.5
mUI
(p-p)
t
OUTCCJ_DC (5)
Cycle to Cycle Jitter for dedicated
clock output
(F
OUT 100 MHz)
175
175
175
175
225
ps (p-p)
Cycle to Cycle Jitter for dedicated
clock output
(F
OUT < 100 MHz)
17.5
17.5
17.5
17.5
22.5
mUI
(p-p)
t
OUTPJ_IO (5), (8)
Period Jitter for clock output on
regular IO (F
OUT  100 MHz)
600
600
600
600
750
ps (p-p)
Period Jitter for clock output on
regular IO (F
OUT < 100 MHz)
60
——
60
——
60
60
—75
mUI
(p-p)
Table 1–20. PLL Specifications for Stratix III Devices (Part 2 of 3)
Symbol
Parameter
C2
C3, I3
C4, I4
C4L, I4L
Unit
V
CCL = 1.1 V
V
CCL = 1.1 V
V
CCL = 1.1 V
V
CCL = 1.1 V
V
CCL = 0.9 V
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max


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