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EP3SE80 Datasheet(PDF) 18 Page - Altera Corporation

Part No. EP3SE80
Description  Stratix III Device Handbook, Volume 2
Download  341 Pages
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Maker  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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EP3SE80 Datasheet(HTML) 18 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
Electrical Characteristics
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
Pin Capacitance
Table 1–10 lists the Stratix III device family pin capacitance.
s
Hot-Socketing
Table 1–11 lists the hot-socketing specifications for Stratix III devices.
Table 1–9. On-Chip Termination Variation after Power-up Calibration
(Note 1)
Symbol
Description
V
CCIO (V)
Commercial
Typical
Unit
dR/dV
OCT variation with voltage without re-calibration
3
0.029
%/mV
2.5
0.036
%/mV
1.8
0.065
%/mV
1.5
0.104
%/mV
1.2
0.177
%/mV
dR/dT
OCT variation with temperature without re-calibration
3
0.294
%/°C
2.5
0.301
%/°C
1.8
0.355
%/°C
1.5
0.344
%/°C
1.2
0.348
%/°C
Note to Table 1–9:
(1) Valid for V
CCIO range of ± 5% and temperature range of 0° to 85° C.
Table 1–10. Pin Capacitance for Stratix III Device Family
Symbol
Parameter
Typical
Unit
C
IOTB
Input capacitance on top and bottom I/O pins
4
pF
C
IOLR
Input capacitance on left and right I/O pins
4
pF
C
CLKTB
Input capacitance on top and bottom
non-dedicated clock input pins
4pF
C
CLKLR
Input capacitance on left and right
non-dedicated clock input pins
4pF
C
OUTFB
Input capacitance on dual-purpose clock
output and feedback pins
5pF
C
CLK1, CCLK3, CCLK8, and
C
CLK10
Input capacitance for dedicated clock input
pins
2pF
Table 1–11. Hot-Socketing Specifications for Stratix III Devices
Symbol
Parameter
Maximum
|I
IOPIN|(DC)
DC current per I/O pin
300
A
|I
IOPIN|(AC)
AC current per I/O pin
8 mA (1)
Note to Table 1–11:
(1) The I/O ramp rate is 10 ns or more. For ramp rates faster than 10 ns, |IIOPIN| = C dv/dt, in which C is I/O pin
capacitance and dv/dt is the slew rate.


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