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EP3SE80 Datasheet(PDF) 49 Page - Altera Corporation

Part No. EP3SE80
Description  Stratix III Device Handbook, Volume 2
Download  341 Pages
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Maker  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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EP3SE80 Datasheet(HTML) 49 Page - Altera Corporation

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Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
1–39
I/O Timing
© July 2010
Altera Corporation
Stratix III Device Handbook, Volume 2
3.0-V
LVCMOS
GCLK
t
su
-0.701
-0.700
-1.003 -1.105 -1.310 -1.265 -1.626 -1.105 -1.310
-1.265
-1.626
ns
t
h
0.827
0.825
1.181
1.306
1.530
1.474
1.829
1.306
1.530
1.474
1.829
ns
GCLK
PLL
t
su
-0.986
-0.986
-1.404 -1.534 -1.772 -1.712 -2.025 -1.534 -1.772
-1.712
-2.025
ns
t
h
1.237
1.237
1.773
1.949
2.231
2.147
2.470
1.949
2.231
2.147
2.470
ns
2.5 V
GCLK
t
su
-0.696
-0.695
-1.012 -1.117 -1.329 -1.284 -1.645 -1.117 -1.329
-1.284
-1.645
ns
t
h
0.822
0.820
1.190
1.318
1.549
1.493
1.848
1.318
1.549
1.493
1.848
ns
GCLK
PLL
t
su
-0.981
-0.981
-1.413 -1.546 -1.791 -1.731 -2.044 -1.546 -1.791
-1.731
-2.044
ns
t
h
1.232
1.232
1.782
1.961
2.250
2.166
2.489
1.961
2.250
2.166
2.489
ns
1.8 V
GCLK
t
su
-0.716
-0.715
-1.052 -1.153 -1.327 -1.282 -1.643 -1.153 -1.327
-1.282
-1.643
ns
t
h
0.844
0.842
1.230
1.354
1.547
1.491
1.846
1.354
1.547
1.491
1.846
ns
GCLK
PLL
t
su
-1.003
-1.003
-1.453 -1.582 -1.789 -1.729 -2.042 -1.582 -1.789
-1.729
-2.042
ns
t
h
1.256
1.256
1.822
1.997
2.248
2.164
2.487
1.997
2.248
2.164
2.487
ns
1.5 V
GCLK
t
su
-0.706
-0.705
-1.029 -1.121 -1.257 -1.212 -1.573 -1.121 -1.257
-1.212
-1.573
ns
t
h
0.834
0.832
1.207
1.322
1.477
1.421
1.776
1.322
1.477
1.421
1.776
ns
GCLK
PLL
t
su
-0.993
-0.993
-1.430 -1.550 -1.719 -1.659 -1.972 -1.550 -1.719
-1.659
-1.972
ns
t
h
1.246
1.246
1.799
1.965
2.178
2.094
2.417
1.965
2.178
2.094
2.417
ns
1.2 V
GCLK
t
su
-0.654
-0.653
-0.952 -1.022 -1.101 -1.056 -1.417 -1.022 -1.101
-1.056
-1.417
ns
t
h
0.782
0.780
1.130
1.223
1.321
1.265
1.620
1.223
1.321
1.265
1.620
ns
GCLK
PLL
t
su
-0.941
-0.941
-1.353 -1.451 -1.563 -1.503 -1.816 -1.451 -1.563
-1.503
-1.816
ns
t
h
1.194
1.194
1.722
1.866
2.022
1.938
2.261
1.866
2.022
1.938
2.261
ns
SSTL-2
CLASS I
GCLK
t
su
-0.625
-0.624
-0.924 -1.006 -1.103 -1.058 -1.419 -1.006 -1.103
-1.058
-1.419
ns
t
h
0.753
0.751
1.102
1.207
1.323
1.267
1.622
1.207
1.323
1.267
1.622
ns
GCLK
PLL
t
su
-0.912
-0.912
-1.325 -1.435 -1.565 -1.505 -1.818 -1.435 -1.565
-1.505
-1.818
ns
t
h
1.165
1.165
1.694
1.850
2.024
1.940
2.263
1.850
2.024
1.940
2.263
ns
SSTL-2
CLASS II
GCLK
t
su
-0.625
-0.624
-0.924 -1.006 -1.103 -1.058 -1.419 -1.006 -1.103
-1.058
-1.419
ns
t
h
0.753
0.751
1.102
1.207
1.323
1.267
1.622
1.207
1.323
1.267
1.622
ns
GCLK
PLL
t
su
-0.912
-0.912
-1.325 -1.435 -1.565 -1.505 -1.818 -1.435 -1.565
-1.505
-1.818
ns
t
h
1.165
1.165
1.694
1.850
2.024
1.940
2.263
1.850
2.024
1.940
2.263
ns
SSTL-18
CLASS I
GCLK
t
su
-0.619
-0.618
-0.912 -1.001 -1.103 -1.056 -1.417 -1.001 -1.103
-1.056
-1.417
ns
t
h
0.747
0.745
1.089
1.199
1.320
1.264
1.615
1.199
1.320
1.264
1.615
ns
GCLK
PLL
t
su
-0.906
-0.906
-1.312 -1.427 -1.562 -1.500 -1.816 -1.427 -1.562
-1.500
-1.816
ns
t
h
1.159
1.159
1.681
1.839
2.018
1.934
2.256
1.839
2.018
1.934
2.256
ns
SSTL-18
CLASS II
GCLK
t
su
-0.619
-0.618
-0.912 -1.001 -1.103 -1.056 -1.417 -1.001 -1.103
-1.056
-1.417
ns
t
h
0.747
0.745
1.089
1.199
1.320
1.264
1.615
1.199
1.320
1.264
1.615
ns
GCLK
PLL
t
su
-0.906
-0.906
-1.312 -1.427 -1.562 -1.500 -1.816 -1.427 -1.562
-1.500
-1.816
ns
t
h
1.159
1.159
1.681
1.839
2.018
1.934
2.256
1.839
2.018
1.934
2.256
ns
Table 1–41. EP3SL50 Column Pins Input Timing Parameters (Part 2 of 3)
I/O
Standard
Clock
Fast Model
C2
C3
C4
C4L
I3
I4
I4L
Units
Industrial
Commercial
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
1.1 V
V
CCL=
0.9 V


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