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EP3SE80 Datasheet(PDF) 46 Page - Altera Corporation

Part No. EP3SE80
Description  Stratix III Device Handbook, Volume 2
Download  341 Pages
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Maker  ALTERA [Altera Corporation]
Homepage  http://www.altera.com
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EP3SE80 Datasheet(HTML) 46 Page - Altera Corporation

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1–36
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
I/O Timing
Stratix III Device Handbook, Volume 2
© July 2010
Altera Corporation
I/O Default Capacitive Loading
Table 1–38 lists the default capacitive loading of various I/O standards.
MINI-LVDS_E_1R
100
120
2.325
2.325
1.02
0
1.1625
MINI-LVDS_E_3R
120
100
170
2.325
2.325
1.02
0
1.1625
RSDS_E_1R
100
120
2.325
2.325
1.02
0
1.1625
RSDS_E_3R
120
100
170
2.325
2.325
1.02
0
1.1625
Notes to Table 1–37:
(1) Hyper transport is not supported by Stratix III devices.
(2) LVPECL outputs are not supported by Stratix III devices.
(3) You can change the Quartus II timing conditions using the Advanced I/O Timing feature.
(4) V
CC is nominally 1.1 V less 50 mV (1.05 V).
(5) Terminated I/O standards require an additional 30 mV IR drop on V
CC (1.02 V).
(6) Terminated I/O standards require an additional 50 mV IR drop on V
CCIO and VCCPD.
Table 1–37. Output Timing Measurement Methodology for Output Pins (Part 3 of 3)
I/O Standard
Loading and Termination
Measurement
Point
R
S
R
D
R
T
R
P
V
CCIO
V
CCPD
V
CC
V
TT
C
L (pF)
V
MEAS (v)
Table 1–38. Default Loading of Various I/O Standards for Stratix III Devices (Part 1 of 2)
I/O Standard
Capacitive
Load
Unit
3.3-V LVTTL
0
pF
3.3-V LVCMOS
0
pF
3.0-V LVTTL
0
pF
3.0-V LVCMOS
0
pF
2.5-V LVTTL/LVCMOS
0
pF
1.8-V LVTTL/LVCMOS
0
pF
1.5-V LVTTL/LVCMOS
0
pF
3.0-V PCI
10
pF
3.0-V PCI-X
10
pF
SSTL-2 CLASS I
0
pF
SSTL-2 CLASS II
0
pF
SSTL-18 CLASS I
0
pF
SSTL-18 CLASS II
0
pF
1.5-V HSTL CLASS I
0
pF
1.5-V HSTL CLASS II
0
pF
1.8-V HSTL CLASS I
0
pF
1.8-V HSTL CLASS II
0
pF
1.2-V HSTL
0
pF
Differential SSTL-2 CLASS I
0
pF
Differential SSTL-2 CLASS II
0
pF
Differential SSTL-18 CLASS I
0
pF


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