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NE555DR Datasheet(PDF) 9 Page - Texas Instruments

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Part No. NE555DR
Description  PRCISION TIMERS
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Maker  TI [Texas Instruments]
Homepage  http://www.ti.com
Logo TI - Texas Instruments

NE555DR Datasheet(HTML) 9 Page - Texas Instruments

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VCC
(5 V to 15 V)
RA
RL
Output
GND
OUT
VCC
CONT
RESET
DISCH
THRES
TRIG
Input
5
8
4
7
6
2
3
1
Pin numbers shown are for the D, JG, P, PS, and PW packages.
NA555, NE555, SA555, SE555
www.ti.com
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
APPLICATION INFORMATION
Monostable Operation
For monostable operation, any of these timers can be connected as shown in Figure 9. If the output is low,
application of a negative-going pulse to the trigger (TRIG) sets the flip-flop (Q goes low), drives the output high,
and turns off Q1. Capacitor C then is charged through RA until the voltage across the capacitor reaches the
threshold voltage of the threshold (THRES) input. If TRIG has returned to a high level, the output of the threshold
comparator resets the flip-flop (Q goes high), drives the output low, and discharges C through Q1.
Figure 9. Circuit for Monostable Operation
Monostable operation is initiated when TRIG voltage falls below the trigger threshold. Once initiated, the
sequence ends only if TRIG is high for at least 10 µs before the end of the timing interval. When the trigger is
grounded, the comparator storage time can be as long as 10 µs, which limits the minimum monostable pulse
width to 10 µs. Because of the threshold level and saturation voltage of Q1, the output pulse duration is
approximately tw = 1.1RAC. Figure 11 is a plot of the time constant for various values of RA and C. The threshold
levels and charge rates both are directly proportional to the supply voltage, VCC. The timing interval is, therefore,
independent of the supply voltage, so long as the supply voltage is constant during the time interval.
Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges
C and reinitiates the cycle, commencing on the positive edge of the reset pulse. The output is held low as long
as the reset pulse is low. To prevent false triggering, when RESET is not used, it should be connected to VCC.
Copyright © 1973–2010, Texas Instruments Incorporated
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Product Folder Link(s): NA555 NE555 SA555 SE555


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