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SN65LVDT2DBVT Datasheet(PDF) 5 Page - Texas Instruments |
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SN65LVDT2DBVT Datasheet(HTML) 5 Page - Texas Instruments |
5 / 22 page DRIVER ELECTRICAL CHARACTERISTICS DRIVER SWITCHING CHARACTERISTICS SN65LVDS1 SN65LVDS2 SN65LVDT2 www.ti.com.................................................................................................................................................... SLLS373K – JULY 1999 – REVISED NOVEMBER 2008 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX UNIT RL = 100 Ω, 2.4 ≤ VCC <3 V 200 350 454 |VOD| Differential output voltage magnitude RL = 100 Ω, 3 ≤ VCC <3.6 V 247 350 454 mV Change in differential output voltage magnitude Δ|VOD| See Figure 2 –50 50 between logic states VOC(SS) Steady-state common-mode output voltage 1.125 1.375 V Change in steady-state common-mode output voltage ΔVOC(SS) See Figure 2 –50 50 mV between logic states VOC(PP) Peak-to-peak common-mode output voltage 25 100 mV VI = 0 V or VCC, No load 2 4 ICC Supply current mA VI = 0 V or VCC, RL = 100 Ω 5.5 8 IIH High-level input current VIH = 5 V 2 20 µA IIL Low-level input current VIL = 0.8 V 2 10 µA VOY or VOZ = 0 V 3 10 IOS Short-circuit output current mA VOD = 0 V 10 IO(OFF) Power-off output current VCC = 1.5 V, VO = 3.6 V –1 1 µA Ci Input capacitance VI = 0.4 Sin (4E6πt)+0.5 V 3 pF (1) The algebraic convention, in which the least positive (most negative) limit is designated as a minimum, is used in this data sheet. (2) All typical values are at 25°C and with a 3.3-V supply. over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 1.5 3.1 ns tPHL Propagation delay time, high-to-low-level output 1.8 3.1 ns RL = 100 Ω, CL = 10 pF, tr Differential output signal rise time 0.6 1 ns See Figure 5 tf Differential output signal fall time 0.7 1 ns tsk(p) Pulse skew (|tPHL - tPLH|) (2) 0.3 ns (1) All typical values are at 25°C and with a 3.3-V supply. (2) tsk(p) is the magnitude of the time difference between the high-to-low and low-to-high propagation delay times at an output. Copyright © 1999–2008, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 |
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