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SN74LV125ADGVRE4 Datasheet(PDF) 2 Page - Texas Instruments |
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SN74LV125ADGVRE4 Datasheet(HTML) 2 Page - Texas Instruments |
2 / 21 page SN54LV125A, SN74LV125A QUADRUPLE BUS BUFFER GATES WITH 3STATE OUTPUTS SCES124L − DECEMBER 1997 − REVISED APRIL 2005 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description/ordering information (continued) To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. FUNCTION TABLE (each buffer) INPUTS OUTPUT OE A OUTPUT Y L H H L LL H X Z logic diagram (positive logic) 2A 2Y 2OE 1A 1Y 1OE 1 2 4 5 3 6 4A 4Y 4OE 3A 3Y 3OE 10 9 13 12 8 11 Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages. |
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