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ADS62P15IRGCT Datasheet(PDF) 1 Page - Texas Instruments |
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ADS62P15IRGCT Datasheet(HTML) 1 Page - Texas Instruments |
1 / 63 page 1 FEATURES APPLICATIONS DESCRIPTION ADS62P15 www.ti.com .................................................................................................................................................... SLAS572B – OCTOBER 2007 – REVISED APRIL 2009 Dual Channel 11-Bits, 125 MSPS ADC With Parallel CMOS/DDR LVDS Outputs Reference also • Maximum Sample Rate: 125 MSPS • 64-QFN Package (9mm × 9mm) • 11-Bit Resolution With No Missing Codes • Pin Compatible 14-bit and 12-bit Family (ADS62P4X/ADS62P2X) • 84 dBc SFDR at Fin = 50 MHz • 67.1 dBFS SNR at Fin = 50 MHz • 92 dB Crosstalk • Wireless Communications Infrastructure • Parallel CMOS and DDR LVDS Output Options • Software Defined Radio • 3.5 dB Coarse Gain and Programmable Fine • Power Amplifier Linearization Gain up to 6 dB for SNR/SFDR Trade-Off • 802.16d/e • Digital Processing Block With: • Medical Imaging – Offset Correction • Radar Systems – Fine Gain Correction, in Steps of 0.05 dB • Test and Measurement Instrumentation – Decimation by 2/4/8 Table 1. ADS62PXX Dual Channel Family – Built-in and Custom Programmable 24-Tap 125 MSPS 105 MSPS 80 MSPS 65 MSPS Low/High /Band Pass Filters ADS62P4X • Supports Sine, LVPECL, LVDS & LVCMOS ADS62P45 ADS62P44 ADS62P43 ADS62P42 (14 bit) Clocks & Amplitude Down to 400 mVPP ADS62P2X ADS62P25 ADS62P24 ADS62P23 ADS62P22 • Clock Duty Cycle Stabilizer (12 bit) (11 bit) ADS62P15 - - - • Internal Reference; Supports External ADS62P15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges. ADS62P15 includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled. Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C). 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Copyright © 2007–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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