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TLV320DAC3120IRHBR Datasheet(PDF) 11 Page - Texas Instruments |
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TLV320DAC3120IRHBR Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 110 page  T0146-10 WCLK BCLK DIN t (WS) h t (WS) h t (BCLK) L t r t f t (DI) S t (BCLK) H t (DI) h t (WS) S t (WS) S TLV320DAC3120 www.ti.com SLAS659 – NOVEMBER 2009 3.4.4 DSP Timing in Slave Mode All specifications at 25°C, DVDD = 1.8 V Note: All timing specifications are measured at characterization but not tested at final test. IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX tH(BCLK) BCLK high period 35 35 ns tL(BCLK) BCLK low period 35 35 ns ts(WS) WCLK setup 8 8 ns th(WS) WCLK hold 8 8 ns ts(DI) DIN setup 8 8 ns th(DI) DIN hold 8 8 ns tr Rise time 4 4 ns tf Fall time 4 4 ns Figure 3-4. DSP Timing in Slave Mode Copyright © 2009, Texas Instruments Incorporated ELECTRICAL SPECIFICATIONS 11 Submit Documentation Feedback Product Folder Link(s): TLV320DAC3120 |
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