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TLV320AIC3254 Datasheet(PDF) 2 Page - Texas Instruments |
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TLV320AIC3254 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 168 page  1.4 Detailed Description TLV320AIC3254 Ultra Low Power Stereo Audio Codec With Embedded miniDSP SLAS549A – SEPTEMBER 2008 – REVISED OCTOBER 2008 www.ti.com The TLV320AIC3254 features two fully programmable miniDSP cores that support application-specific algorithms in the record and/or the playback path of the device. The miniDSP cores are fully software controlled. Target algorithms, like active noise cancellation, acoustic echo cancellation or advanced DSP filtering are loaded into the device after power-up. Extensive Register based control of power, input/output channel configuration, gains, effects, pin-multiplexing and clocks is included, allowing the device to be precisely targeted to its application. Combined with the advanced PowerTune technology, the device can cover operations from 8 kHz mono voice playback to audio stereo 192kHz DAC playback, making it ideal for portable battery-powered audio and telephony applications. The record path of the TLV320AIC3254 covers operations from 8kHz mono to 192kHz stereo recording, and contains programmable input channel configurations covering single-ended and differential setups, as well as floating or mixing input signals. It also includes a digitally-controlled stereo microphone preamplifier and integrated microphone bias. Digital signal processing blocks can remove audible noise that may be introduced by mechanical coupling, e.g. optical zooming in a digital camera. The playback path offers signal-processing blocks for filtering and effects, and supports flexible mixing of DAC and analog input signals as well as programmable volume controls. The playback path contains two high-power output drivers as well as two fully-differential outputs. The high-power outputs can be configured in multiple ways, including stereo and mono BTL. The integrated PowerTune technology allows the device to be tuned to just the right power-performance trade-off. Mobile applications frequently have multiple use cases requiring very low power operation while being used in a mobile environment. When used in a docked environment power consumption typically is less of a concern, while minimizing noise is important. With PowerTune, the TLV320AIC3254 addresses both cases. The voltage supply range for the TLV320AIC3254 for analog is 1.5V–1.95V, and for digital it is 1.26V–1.95V. To ease system-level design, LDOs are integrated to generate the appropriate analog or digital supply from input voltages ranging from 1.8V to 3.6V. Digital I/O voltages are supported in the range of 1.1V–3.6V. The required internal clock of the TLV320AIC3254 can be derived from multiple sources, including the MCLK pin, the BCLK pin, the GPIO pin or the output of the internal PLL, where the input to the PLL again can be derived from the MCLK pin, the BCLK or GPIO pins. Although using the PLL ensures the availability of a suitable clock signal, it is not recommended for the lowest power settings. The PLL is highly programmable and can accept available input clocks in the range of 512kHz to 50MHz. The device is available in the 5-mm × 5-mm, 32-pin QFN package. Introduction 2 Submit Documentation Feedback |
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