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LM3S8733-IQN50-A2 Datasheet(PDF) 4 Page - Texas Instruments |
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LM3S8733-IQN50-A2 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 616 page 6.1.2 Reset Control ................................................................................................................ 68 6.1.3 Power Control ............................................................................................................... 71 6.1.4 Clock Control ................................................................................................................ 73 6.1.5 System Control ............................................................................................................. 78 6.2 Initialization and Configuration ....................................................................................... 79 6.3 Register Map ................................................................................................................ 80 6.4 Register Descriptions .................................................................................................... 81 7 Hibernation Module .............................................................................................. 135 7.1 Block Diagram ............................................................................................................ 136 7.2 Functional Description ................................................................................................. 136 7.2.1 Register Access Timing ............................................................................................... 136 7.2.2 Clock Source .............................................................................................................. 137 7.2.3 Battery Management ................................................................................................... 138 7.2.4 Real-Time Clock .......................................................................................................... 138 7.2.5 Non-Volatile Memory ................................................................................................... 139 7.2.6 Power Control ............................................................................................................. 139 7.2.7 Initiating Hibernate ...................................................................................................... 139 7.2.8 Interrupts and Status ................................................................................................... 140 7.3 Initialization and Configuration ..................................................................................... 140 7.3.1 Initialization ................................................................................................................. 140 7.3.2 RTC Match Functionality (No Hibernation) .................................................................... 140 7.3.3 RTC Match/Wake-Up from Hibernation ......................................................................... 141 7.3.4 External Wake-Up from Hibernation .............................................................................. 141 7.3.5 RTC/External Wake-Up from Hibernation ...................................................................... 141 7.4 Register Map .............................................................................................................. 141 7.5 Register Descriptions .................................................................................................. 142 8 Internal Memory ................................................................................................... 155 8.1 Block Diagram ............................................................................................................ 155 8.2 Functional Description ................................................................................................. 155 8.2.1 SRAM Memory ............................................................................................................ 155 8.2.2 Flash Memory ............................................................................................................. 156 8.3 Flash Memory Initialization and Configuration ............................................................... 157 8.3.1 Flash Programming ..................................................................................................... 157 8.3.2 Nonvolatile Register Programming ............................................................................... 158 8.4 Register Map .............................................................................................................. 159 8.5 Flash Register Descriptions (Flash Control Offset) ......................................................... 159 8.6 Flash Register Descriptions (System Control Offset) ...................................................... 167 9 General-Purpose Input/Outputs (GPIOs) ........................................................... 180 9.1 Functional Description ................................................................................................. 180 9.1.1 Data Control ............................................................................................................... 181 9.1.2 Interrupt Control .......................................................................................................... 182 9.1.3 Mode Control .............................................................................................................. 183 9.1.4 Commit Control ........................................................................................................... 183 9.1.5 Pad Control ................................................................................................................. 183 9.1.6 Identification ............................................................................................................... 184 9.2 Initialization and Configuration ..................................................................................... 184 9.3 Register Map .............................................................................................................. 185 9.4 Register Descriptions .................................................................................................. 187 June 22, 2010 4 Texas Instruments-Production Data Table of Contents |
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