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ELECTRICAL CHARACTERISTICS

TIMING REQUIREMENTS

CDCU2A877

SCAS827A – AUGUST 2006 – REVISED JUNE 2007

over recommended operating free-air temperature range

PARAMETERLow-level output voltage

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Input (cl inputs)

1.7 V

–1.2

V

1.7 V to

VDDQ

1.9 V

– 0.2

High-level output voltage

V

1.7 V

1.1

0.1

Low-level output voltage

V

1.7 V

0.6

Low-level output current, disabled

1.7 V

100

μA

1.7 V

0.6

V

CK, CK

1.9 V

±250

Input current

μA

OE, OS, FBIN, FBIN

1.9 V

±10

CK and CK = L

1.9 V

500

μA

CK and CK = 410 MHz,

All outputs are open

1.9 V

300

mA

(not connected to a PCB)

(2)

All outputs are loaded with 2 pF

and 120-

Ω termination resistor,

1.9 V

325

mA

CK and CK = 410 MHz

CK, CK

1.8 V

2

3

Input capacitance

pF

FBIN, FBIN

1.8 V

2

3

CK, CK

1.8 V

0.25

Change in input

pF

current

FBIN, FBIN

1.8 V

0.25

(1)

(2)

over recommended operating free-air temperature range

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

125

410

MHz

160

410

MHz

Duty cycle, input clock

40%

60%

6

μs

(1)

The PLL must be able to handle spread spectrum induced skew.

(2)

Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other

timing parameters (used for low speed system debug).

(3)

Application clock frequency indicates a range over which the PLL must meet all timing parameters.

(4)

Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal,

required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic

low state, enter the power-down mode, and later return to active operation. CK and CK may be left floating after they have been driven

low for one complete clock cycle.

6

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