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NIS5132MN2TXG Datasheet(PDF) 4 Page - ON Semiconductor |
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NIS5132MN2TXG Datasheet(HTML) 4 Page - ON Semiconductor |
4 / 12 page NIS5132 http://onsemi.com 4 ELECTRICAL CHARACTERISTICS (Unless otherwise noted: VCC = 12 V, CL = 100 mF, dv/dt pin open, RLIMIT = 10 W, Tj = 25°C unless otherwise noted.) Characteristics Symbol Min Typ Max Unit POWER FET Delay Time (enabling of chip to ID = 100 mA with 1 A resistive load) Tdly 220 ms Kelvin ON Resistance (Note 4) TJ = 80°C (Note 5) RDSon 35 44 95 55 mW Off State Output Voltage (VCC = 18 Vdc, VGS = 0 Vdc, RL = R) Voff 190 300 mV Output Capacitance (VDS = 12 Vdc, VGS = 0 Vdc, f = 1 MHz) 250 pF Continuous Current (TA = 25°C, 0.5 in2 pad) (Note 5) (TA = 80°C, minimum copper) ID ID 3.6 1.7 A THERMAL LATCH Shutdown Temperature (Note 5) TSD 150 175 200 °C Thermal Hysteresis (Decrease in die temperature for turn on, does not apply to latching parts) THyst 45 °C UNDER/OVERVOLTAGE PROTECTION Output Clamping Voltage (Overvoltage Protection) (VCC = 18 V) VClamp 14 15 16.2 V Undervoltage Lockout (Turn on, voltage going high) VUVLO 7.7 8.5 9.3 V UVLO Hysteresis VHyst − 0.80 − V CURRENT LIMIT Kelvin Short Circuit Current Limit (RLimit = 15.4 W, Note 6) ILim−SS 2.75 3.44 4.25 A Kelvin Overload Current Limit (RLimit = 15.4 W, Note 6) ILim−OL 4.6 A dv/dt CIRCUIT Output Voltage Ramp Time (Enable to VOUT = 11.7 V) tslew 0.5 0.9 1.8 ms Maximum Capacitor Voltage Vmax VCC V ENABLE/FAULT Logic Level Low (Output Disabled) Vin−low 0.35 0.58 0.81 V Logic Level Mid (Thermal Fault, Output Disabled) Vin−mid 0.82 1.4 1.95 V Logic Level High (Output Enabled) Vin−high 1.96 2.64 3.30 V High State Maximum Voltage Vin−max 3.40 4.30 5.2 V Logic Low Sink Current (Venable = 0 V) Iin−low −17 −25 mA Logic High Leakage Current for External Switch (Venable = 3.3 V) Iin−leak 1.0 mA Maximum Fanout for Fault Signal (Total number of chips that can be connected to this pin for simultaneous shutdown) Fan 3.0 Units TOTAL DEVICE Bias Current (Operational) IBias 1. 8 2.5 mA Bias Current (Shutdown) IBias 1.0 mA Minimum Operating Voltage (Notes 5 and 7) Vmin 7.6 V 4. Pulse test: Pulse width 300 us, duty cycle 2%. 5. Verified by design. 6. Refer to explanation of short circuit and overload conditions in application note AND8140. 7. Device will shut down prior to reaching this level based on actual UVLO trip point. |
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