Electronic Components Datasheet Search |
|
SN74LV594APW Datasheet(PDF) 7 Page - Texas Instruments |
|
|
SN74LV594APW Datasheet(HTML) 7 Page - Texas Instruments |
7 / 20 page SN54LV594A, SN74LV594A 8BIT SHIFT REGISTERS WITH OUTPUT REGISTERS SCLS413I − APRIL 1998 − REVISED APRIL 2005 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C SN54LV594A SN74LV594A UNIT MIN MAX MIN MAX MIN MAX UNIT tw Pulse duration RCLK or SRCLK high or low 7 7.5 7.5 ns tw Pulse duration RCLR or SRCLR low 6 6.5 6.5 ns SER before SRCLK ↑ 5.5 5.5 5.5 SRCLK ↑ before RCLK↑† 8 9 9 tsu Setup time SRCLR low before RCLK ↑ 8.5 9.5 9.5 ns tsu Setup time SRCLR high (inactive) before SRCLK ↑ 6 6.8 6.8 ns RCLR high (inactive) before RCLK ↑ 6.7 7.6 7.6 th Hold time SER after SRCLK ↑ 1.5 1.5 1.5 ns † This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C SN54LV594A SN74LV594A UNIT MIN MAX MIN MAX MIN MAX UNIT tw Pulse duration RCLK or SRCLK high or low 5.5 5.5 5.5 ns tw Pulse duration RCLR or SRCLR low 5 5 5 ns SER before SRCLK ↑ 3.5 3.5 3.5 SRCLK ↑ before RCLK↑† 8 8.5 8.5 tsu Setup time SRCLR low before RCLK ↑ 8 9 9 ns tsu Setup time SRCLR high (inactive) before SRCLK ↑ 4.2 4.8 4.8 ns RCLR high (inactive) before RCLK ↑ 4.6 5.3 5.3 th Hold time SER after SRCLK ↑ 1.5 1.5 1.5 ns † This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C SN54LV594A SN74LV594A UNIT MIN MAX MIN MAX MIN MAX UNIT tw Pulse duration RCLK or SRCLK high or low 5 5 5 ns tw Pulse duration RCLR or SRCLR low 5.2 5.2 5.2 ns SER before SRCLK ↑ 3 3 3 SRCLK ↑ before RCLK↑† 5 5 5 tsu Setup time SRCLR low before RCLK ↑ 5 5 5 ns tsu Setup time SRCLR high (inactive) before SRCLK ↑ 2.9 3.3 3.3 ns RCLR high (inactive) before RCLK ↑ 3.2 3.7 3.7 th Hold time SER after SRCLK ↑ 2 2 2 ns † This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. |
Similar Part No. - SN74LV594APW |
|
Similar Description - SN74LV594APW |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |