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DESCRIPTION (CONTINUED)

G

G

1A

1B

2A

2B

3A

3B

4A

4B

4

12

2

1

6

7

10

9

14

15

3

5

11

13

1Y

2Y

3Y

4Y

’LVDS32 logic diagram

(positive logic)

1A

1B

2A

2B

3A

3B

4A

4B

4

12

2

1

6

7

10

9

14

15

3

5

11

13

1Y

2Y

3Y

4Y

3,4EN

1,2EN

SN65LVDS3486D logic diagram

(positive logic)

1A

1B

2A

2B

8

7

6

5

2

3

1Y

2Y

SN65LVDS9637D logic diagram

(positive logic)

SN55LVDS32, SN65LVDS32

SN65LVDS3486, SN65LVDS9637

SLLS262Q – JULY 1997 – REVISED JULY 2007

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

The SN65LVDS32, SN65LVDS3486, and SN65LVDS9637 are characterized for operation from –40

°C to 85°C.

The SN55LVDS32 is characterized for operation from –55

°C to 125°C.

Table 1. Maximum Recommended Operating Speeds

Part Number

All Rx Active

SN65LVDS32

100 Mbps

SN65LVDS3486

100 Mbps

SN65LVDS9637

150 Mbps

AVAILABLE OPTIONS

SMALL OUTLINE

CHIP CARRIER

CERAMIC DIP

FLAT PACK

MSOP

(FK)

(J)

(W)

(D)

(PW)

SN65LVDS32D

SN65LVDS32PW

—

—

—

—

SN65LVDS3486D

—

—

—

—

–40

°C to 85°C

SN65LVDS9637D

SN65LVDS9637DGN

—

—

—

—

SN65LVDS9637DGK

—

—

—

–55

°C to

SNJ55LVDS32W

—

—

—

SNJ55LVDS32FK

SNJ55LVDS32J

125

°C

SN55LVDS32W

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

2

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