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NCP5392MNR2G Datasheet(PDF) 11 Page - ON Semiconductor |
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NCP5392MNR2G Datasheet(HTML) 11 Page - ON Semiconductor |
11 / 32 page NCP5392 http://onsemi.com 11 ELECTRICAL CHARACTERISTICS (Unless otherwise stated: 0°C < TA < 85°C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Unit Max Typ Min Test Conditions IMON Output source current (Note 3) Vout = 1 V 300 − − mA Output sink current (Note 3) Vout = 0.3 V 300 − − mA Maximum Clamp Voltage VDRP Voltage = 2 V, RLOAD = 100 k − − 1.15 V OSCILLATOR Switching Frequency Range (Note 3) 100 − 1000 kHz Switching Frequency Accuracy 2− or 4−Phase ROSC = 49.9 kW 200 − 224 kHz ROSC = 24.9 kW 374 − 414 ROSC = 10 kW 800 − 978 Switching Frequency Accuracy 3−Phase ROSC = 49.9 kW 191 − 234 kHz ROSC = 24.9 kW 354 − 434 ROSC = 10 kW 755 − 1000 ROSC Output Voltage 1.95 2.01 2.065 V MODULATORS (PWM Comparators) Minimum Pulse Width FSW = 800 KHz − 30 − ns Propagation Delay ±20 mV of Overdrive − 10 − ns 0% Duty Cycle COMP Voltage when the PWM Outputs Remain LO − 1.3 − V 100% Duty Cycle COMP Voltage when the PWM Outputs Remain HI − 2.3 − V PWM Ramp Duty Cycle Matching Between Any Two Phases − 90 − % PWM Phase Angle Error (Note 3) Between Adjacent Phases 15 − 15 ° VR_RDY (POWER GOOD) OUTPUT VR_RDY Output Saturation Voltage IPGD = 10 mA, − − 0.4 V VR_RDY Rise Time (Note 3) External Pullup of 1 kW to 1.25 V, CTOT = 45 pF, DVo = 10% to 90% − 100 150 ns VR_RDY Output Voltage at Powerup (Note 3) VR_RDY Pulled up to 5 V via 2kW, tR(VCC) ≤ 3 x tR(5V) 100 ms ≤ tR(VCC) ≤ 20 ms − − 1.0 V VR_RDY High – Output Leakage Current (Note 3) VR_RDY = 5.5 V via 1 K − − 0.2 mA VR_RDY Upper Threshold Voltage VCore Increasing, DAC = 1.3 V − 310 270 mV Below DAC VR_RDY Lower Threshold Voltage VCore Decreasing DAC = 1.3 V 410 370 mV Below DAC VR_RDY Rising Delay VCore Increasing − 500 − ms VR_RDY Falling Delay VCore Decreasing − 5 − ms PWM OUTPUTS Output High Voltage Sourcing 500 mA 3.0 − − V Mid Output Voltage 1.4 1.5 1.6 V Output Low Voltage Sinking 500 mA − − 0.7 V Delay + Fall Time (Note 3) CL (PCB) = 50 pF, DVo = VCC to GND − 10 15 ns Delay + Rise Time (Note 3) CL (PCB) = 50 pF, DVo = GND to VCC − 10 15 ns 3. Guaranteed by design, not tested in production. |
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