EPF10K50S datasheet(29/34 Pages) ALTERA

Part #	EPF10K50S

Description	1. Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

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Manufacturer	ALTERA [Altera Corporation]

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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

1–29

Timing Information

Altera Corporation

Configuration Handbook (Complete Two-Volume Set)

Timing Information

Figure 1–7 shows the configuration timing waveform when using an enhanced

configuration device.

Table 1–14 defines the timing parameters when using the enhanced configuration

devices.

f For more information about the flash memory (external flash interface) timing, refer

to the appropriate flash data sheet on the Altera website at www.altera.com.

■

For Micron flash-based EPC4, refer to the Micron MT28F400B3 Data Sheet Flash

Memory Used in EPC4 Devices at www.micron.com.

■

For Sharp flash-based EPC16, refer to the Sharp LHF16J06 Data Sheet Flash Memory

Used in EPC16 Devices at www.sharpsma.com.

■

For Intel flash-based EPC4 and EPC16, refer to Intel Flash 28F016B3 at

www.intel.com.

Figure 1–7. Configuration Timing Waveform Using an Enhanced Configuration Device

Notes to Figure 1–7:

(1) The enhanced configuration device will drive DCLK low after configuration.

(2) The enhanced configuration device will drive DATA[] high after configuration.

Byte0

Byte1

Byte2 Byte3

Byten

Tri-State

User Mode

(2)

tOEZX

tPOR

tCH

tCL

tDSU

tCO

tDH

Tri-State

OE/nSTATUS

nCS/CONF_DONE

DCLK

DATA[7..0]

User I/O

INIT_DONE

nINIT_CONF or VCC/nCONFIG

Table 1–14. Enhanced Configuration Device Configuration Parameters (Part 1 of 2)

Symbol

Parameter

Condition

Min

Typ

Max

Unit

fDCLK

DCLK

frequency

40% duty cycle

—

66.7

MHz

tDCLK

DCLK

period

—

15

—

ns

tHC

DCLK

duty cycle high time

40% duty cycle

6

—

ns

tLC

DCLK

duty cycle low time

40% duty cycle

6

—

ns

tCE

OE

to first DCLK delay

—

40

—

ns

tOE

OE

to first DATA available

—

40

—

ns

tOH

DCLK

rising edge to DATA change

—

(1)

——

ns

tCF (2)

OE

assert to DCLK disable delay

—

277

—

ns

tDF (2)

OE

assert to DATA disable delay

—

277

—

ns

tRE (3)

DCLK

rising edge to OE

—60

—

ns

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