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SN65LVDS2DBVRG4 Datasheet(PDF) 8 Page - Texas Instruments |
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SN65LVDS2DBVRG4 Datasheet(HTML) 8 Page - Texas Instruments |
8 / 21 page VID VO 10 pF, 2 Places 15 pF 100 Ω† 1000 Ω 1000 Ω 100 Ω VIC VID VO VID VO VIT+ 0 V −100 mV 100 mV 0 V VIT− † Remove for testing LVDT device. NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of < 1 ns. NOTE: Input signal of 3 Mpps, duration of 167 ns, and transition time of <1 ns. + − SN65LVDS1 SN65LVDS2 SN65LVDT2 SLLS373K – JULY 1999 – REVISED NOVEMBER 2008.................................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Figure 4. VIT+ and VIT- Input Voltage Threshold Test Circuit and Definitions 8 Submit Documentation Feedback Copyright © 1999–2008, Texas Instruments Incorporated Product Folder Link(s): SN65LVDS1 SN65LVDS2 SN65LVDT2 |
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