1

8

2

7

3

6

4

5

D0

Q0

Q1

V

CC

D0

D1

GND

D1

LVPECL

LVTTL

+

+

+

+

+

SN65EPT23

www.ti.com

SLLS969 – NOVEMBER 2009

3.3V ECL Differential LVPECL/LVDS to LVTTL/LVCMOS Translator

Check for Samples: SN65EPT23

1

FEATURES

PINOUT ASSIGNMENT

•

Dual 3.3 V Differential LVPECL/LVDS to

LVTTL/LVCMOS Buffer Translator

•

24 mA LVTTL Ouputs

•

Operating Range

–

–

GND = 0 V

•

Support for Clock Frequencies > 300 MHz

•

2.0 ns Typical Propagation Delay

•

Built-in Temperature Compensation

•

Drop in Compatible to MC100EPT23

APPLICATIONS

•

Data and Clock Transmission Over Backplane

Table 1. PIN DESCRIPTION

•

Signaling Level Conversion for Clock or Data

PIN

FUNCTION

LVTTL/LVCMOS Outputs

DESCRIPTION

Differential LVPECL/LVDS/CML Inputs

The SN65EPT23 is a low power dual LVPECL/LVDS

Positive Supply

to LVTTL/LVCMOS translator device. The device

includes circuitry to maintain inputs at Vcc/2 when left

GND

Ground

open. The SN65EPT23 is housed in an industry

EP

Exposed pad must be connected to a

standard SOIC-8 package and is also available in

sufficient thermal conduit. Electrically

connect to the most negative supply or

TSSOP-8 option.

leave floating open.

PART NUMBER

PART MARKING

PACKAGE

LEAD FINISH

SN65EPT23D/DR

EPT23

SOIC

NiPdAu

SN65EPT23DGK/DGKR

SSTI

MSOP

NiPdAu

(1)

Leaded device option not initially available; contact TI sales representative for further information.

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Copyright © 2009, Texas Instruments Incorporated

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.