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DRV8432DKD Datasheet(PDF) 11 Page - Texas Instruments |
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DRV8432DKD Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 32 page  DRV8412 DRV8432 www.ti.com SLES242C – DECEMBER 2009 – REVISED MAY 2010 Bootstrap Capacitor Under Voltage Protection ERROR REPORTING When the device runs at a low switching frequency The FAULT and OTW pins are both active-low, (e.g. less than 10 kHz with a 100-nF bootstrap open-drain outputs. Their function is for capacitor), the bootstrap capacitor voltage might not protection-mode signaling to a PWM controller or be able to maintain a proper voltage level for the other system-control device. high-side gate driver. A bootstrap capacitor Any fault resulting in device shutdown, such as undervoltage protection circuit (BST_UVP) will overtemperatue shut down, overcurrent shut-down, or prevent potential failure of the high-side MOSFET. undervoltage protection, is signaled by the FAULT pin When the voltage on the bootstrap capacitors is less going low. Likewise, OTW goes low when the device than the required value for safe operation, the junction temperature exceeds 125°C (see Table 1). DRV8412/32 will initiate bootstrap capacitor recharge sequences (turn off high side FET for a short period) Table 1. Protection Mode Signal Descriptions until the bootstrap capacitors are properly charged for safe operation. This function may also be activated FAULT OTW DESCRIPTION when PWM duty cycle is too high (e.g. less than 20 0 0 Overtemperature warning and ns off time at 10 kHz). Note that bootstrap capacitor (overtemperature shut down or overcurrent shut down or undervoltage protection) occurred might not be able to be charged if no load or extremely light load is presented at output during 0 1 Overcurrent shut-down or GVDD undervoltage protection occurred BST_UVP operation, so it is recommended to turn on the low side FET for at least 50 ns for each PWM 1 0 Overtemperature warning cycle to avoid BST_UVP operation if possible. 1 1 Device under normal operation For applications with lower than 10 kHz switching TI recommends monitoring the OTW signal using the frequency and not to trigger BST_UVP protection, a system microcontroller and responding to an OTW larger bootstrap capacitor can be used (e.g., 1 µF signal by reducing the load current to prevent further cap for 800 Hz operation). When using a bootstrap heating of the device resulting in device cap larger than 220 nF, it is recommended to add 5 Ω overtemperature shutdown (OTSD). resistors between 12V GVDD power supply and GVDD_X pins to limit the inrush current on the To reduce external component count, an internal internal bootstrap circuitry. pullup resistor to VREG (3.3 V) is provided on both FAULT and OTW outputs. Level compliance for 5-V Overcurrent (OC) Protection logic can be obtained by adding external pull-up resistors to 5 V (see the Electrical Characteristics The DRV8412/32 have independent, fast-reacting section of this data sheet for further specifications). current detectors with programmable trip threshold (OC threshold) on all high-side and low-side DEVICE PROTECTION SYSTEM power-stage FETs. There are two settings for OC protection through mode selection pins: The DRV8412/32 contain advanced protection cycle-by-cycle (CBC) current limiting mode and OC circuitry carefully designed to facilitate system latching (OCL) shut down mode. integration and ease of use, as well as to safeguard the device from permanent failure due to a wide In CBC current limiting mode, the detector outputs range of fault conditions such as short circuits, are monitored by two protection systems. The first overcurrent, overtemperature, and undervoltage. The protection system controls the power stage in order to DRV8412/32 respond to a fault by immediately prevent the output current from further increasing, setting the half bridge outputs in a high-impedance i.e., it performs a CBC current-limiting function rather (Hi-Z) state and asserting the FAULT pin low. In than prematurely shutting down the device. This situations other than overcurrent or overtemperature, feature could effectively limit the inrush current during the device automatically recovers when the fault motor start-up or transient without damaging the condition has been removed or the gate supply device. During short to power and short to ground voltage has increased. For highest possible reliability, conditions, the current limit circuitry might not be able reset the device externally no sooner than 1 second to control the current to a proper level, a second after the shutdown when recovering from an protection system triggers a latching shutdown, overcurrent shut down (OCSD) or OTSD fault. resulting in the related half bridge being set in the high-impedance (Hi-Z) state. Current limiting and overcurrent protection are independent for half-bridges A, B, C, and, D, respectively. Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): DRV8412 DRV8432 |
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