 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
DAC8718SPAG Datasheet(PDF) 4 Page - Texas Instruments |
|
|
||||||||||||||||||||||||||||||
DAC8718SPAG Datasheet(HTML) 4 Page - Texas Instruments |
|
|
4 / 62 page  DAC8718 SBAS467A – MAY 2009 – REVISED DECEMBER 2009 www.ti.com ELECTRICAL CHARACTERISTICS: Dual-Supply (continued) All specifications at TA = TMIN to TMAX, AVDD = +16.5V, AVSS = –16.5V, IOVDD = DVDD = +5V, REF-A and REF-B = +5V, gain = 6, AGND-x = DGND = 0V, data format = straight binary, and Offset DAC A and Offset DAC B are at default values (1), unless otherwise noted. DAC8718 PARAMETER CONDITIONS MIN TYP MAX UNIT ANALOG OUTPUT (VOUT-0 to VOUT-7) (4) VREF = +5V –15 +15 V Voltage output(5) VREF = +1.5V –4.5 +4.5 V Output impedance Code = 8000h 0.5 Ω Short-circuit current(6) ±8 mA Load current See Figure 37 ±3 mA TA = +25°C, device operating for 500 hours, full-scale output 3.4 ppm of FSR Output drift vs time TA = +25°C, device operating for 1000 hours, full-scale output 4.3 ppm of FSR Capacitive load stability 500 pF To 0.03% of FSR, CL = 200pF, RL= 10kΩ, code from 0000h 10 μs to FFFFh and FFFFh to 0000h To 1 LSB, CL = 200pF, RL = 10kΩ, code from 0000h to Settling time 15 μs FFFFh and FFFFh to 0000h To 1 LSB, CL = 200pF, RL = 10kΩ, code from 7F00h to 6 μs 8100h and 8100h to 7F00h Slew rate (7) 6 V/ μs Power-on delay(8) From IOVDD ≥ +1.8V and DVDD ≥ +2.7V to CS low 200 μs Power-down recovery time 60 μs Digital-to-analog glitch(9) Code from 7FFFh to 8000h and 8000h to 7FFFh 4 nV-s Glitch impulse peak amplitude Code from 7FFFh to 8000h and 8000h to 7FFFh 5 mV Channel-to-channel isolation(10) VREF = 4VPP, f = 1kHz 88 dB DACs in the same group 7.5 nV-s DAC-to-DAC crosstalk(11) DACs among different groups 1 nV-s Digital crosstalk(12) 1 nV-s Digital feedthrough(13) 1 nV-s TA = +25°C at 10kHz, gain = 6 200 nV/ √Hz Output noise TA = +25°C at 10kHz, gain = 4 130 nV/ √Hz 0.1Hz to 10Hz, gain = 6 20 μVPP Power-supply rejection(14) AVDD = ±15.5V to ±16.5V 0.05 LSB (4) Specified by design. (5) The analog output range of VOUT-0 to VOUT-7 is equal to (6 × VREF – 5 × OUTPUT_OFFSET_DAC) for gain = 6. The maximum value of the analog output must not be greater than (AVDD – 0.5V), and the minimum value must not be less than (AVSS + 0.5V). All specifications are for a ±16.5V power supply and a ±15V output, unless otherwise noted. (6) When the output current is greater than the specification, the current is clamped at the specified maximum value. (7) Slew rate is measured from 10% to 90% of the transition when the output changes from 0 to full-scale. (8) Power-on delay is defined as the time from when the supply voltages reach the specified conditions to when CS goes low, for valid digital communication. (9) Digital-to-analog glitch is defined as the amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between 7FFFh and 8000h in straight binary format. (10) Channel-to-channel isolation refers to the ratio of the signal amplitude at the output of one DAC channel to the amplitude of the sinusoidal signal on the reference input of another DAC channel. It is expressed in dB and measured at midscale. (11) DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC as a result of both the full-scale digital code and subsequent analog output change at another DAC. It is measured with LDAC tied low and expressed in nV-s. (12) Digital crosstalk is the glitch impulse transferred to the output of one converter as a result of a full-scale code change in the DAC input register of another converter. It is measured when the DAC output is not updated, and is expressed in nV-s. (13) Digital feedthrough is the glitch impulse injected to the output of a DAC as a result of a digital code change in the DAC input register of the same DAC. It is measured with the full-scale digital code change without updating the DAC output, and is expressed in nV-s. (14) The output must not be greater than (AVDD – 0.5V) and not less than (AVSS + 0.5V). 4 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated Product Folder Link(s): DAC8718 |
Similar Part No. - DAC8718SPAG |
|
Similar Description - DAC8718SPAG |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.COM |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
